AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 58
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AT32UC3C2512C
Manufacturer Part Number
AT32UC3C2512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2512C
Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2512C-A2UR
Manufacturer:
YAGEO
Quantity:
60 000
Company:
Part Number:
AT32UC3C2512C-U
Manufacturer:
ATMEL
Quantity:
125
Company:
Part Number:
AT32UC3C2512C-Z2ZR
Manufacturer:
Atmel
Quantity:
1 499
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (5Mb)
58
AVR32
The following fields exist in PCCR, see
Table 7-1.
Bit
23:18
17:12
10:8
6:4
3
2
1
0
Other
Access
Read/write
Read/write
Read/write
Read/write
Read/write
Read-0/write
Read-0/write
Read/write
Read-0/write-
0
Performance counter control register
Name
CONF1
CONF0
F
IE
S
C
R
E
-
Description
Configures which events to count with PCNT1. See Table 7-2 for a
legend.
Configures which events to count with PCNT0. See Table 7-2 for a
legend.
Interrupt flag. If read as 1, the corresponding overflow has
occurred. Bit 8 corresponds to PCCNT.
Bit 9 corresponds to PCNT0.
Bit 10 corresponds to PCNT1.
Flags are cleared by writing a 1 to the flag.
Interrupt enable. If set, an overflow of the corresponding counter
will cause an interrupt request.
Bit 4 corresponds to PCCNT.
Bit 5 corresponds to PCNT0.
Bit 6 corresponds to PCNT1.
Clock counter scaler. If set, the clock counter increments once
every 64’th clock cycle. This expands the period-to-overflow to 2
cycles.
Clock counter reset. If written to 1, the clock counter will be reset.
Performance counter reset. If written to 1, all three counters will be
reset.
Clock counter enable. If set, all three counters will count their
configured events. If cleared, the counters are disabled and will
not count.
Unused. Read as 0. Should be written as 0.
Table 7-1 on page
58.
32000D–04/2011
38
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