AT32UC3C264C Atmel Corporation, AT32UC3C264C Datasheet - Page 75

• Manufacturer Part Number: AT32UC3C264C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C264C

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.5
32002F–03/2010
Multiply instructions
Table 8-1.
These instructions require one pass through the multiplier array and produce a 32- or 48-bit
result. For mulrndhh, a rounding value of 0x8000 is added to the product producing the final
result. This group does not set any flags, except for the mulsat instructions which set Q if satura-
tion occurred.
Table 8-2.
movh
csrf
csrfcz
ssrf
sr{cond4}
Mnemonics
mul
mulhh.w
mulnhh.w
mulnwh.d
mulwh.d
mulsathh.h
mulsathh.w
mulsatwh.w
mulsatrndhh.h
mulsatrndwh.
w
ALU instructions
Multiply instructions
E
C
C
C
C
E
E
E
E
E
E
E
E
E
E
E
Rd, imm
b5
b5
b5
Rd
Operands
Rd, Rx, Ry
Rd, Rs, imm
Rd, Rx<part>,
Ry<part>
Rd, Rx<part>,
Ry<part>
Rd, Rx, Ry<part>
Rd, Rx, Ry<part>
Rd, Rx<part>,
Ry<part>
Rd, Rx<part>,
Ry<part>
Rd, Rx, Ry<part>
Rd, Rx<part>,
Ry<part>
Rd, Rx, Ry<part>
Load immediate into high halfword of register.
CPU revision 2 and higher only.
Clear status register flag.
Set status register flag.
Conditionally set register to true or false
Description
Multiply.
(32 ← 32 x 32)
Signed Multiply of halfwords.
(32 ← 16 x 16)
Signed Multiply of halfwords.
(32 ← 16 x 16)
Signed Multiply, word and halfword.
(48 ← 32 x 16)
Signed Multiply, word and halfword.
(48 ← 32 x 16)
Fractional signed multiply with saturation.
Return halfword.
(16 ← 16 x 16)
Fractional signed multiply with saturation.
Return word.
(32 ← 16 x 16)
Fractional signed multiply with saturation.
Return word.
(32 ← 32 x 16)
Signed multiply with rounding. Return
halfword.
(16 ← 16 x 16)
Signed multiply with rounding. Return
halfword.
(32 ← 32 x 16)
Copy status register flag to C and Z.
Multiply immediate.
AVR32
Issue
latency
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