AT32UC3C264C Atmel Corporation, AT32UC3C264C Datasheet - Page 165
AT32UC3C264C
Manufacturer Part Number
AT32UC3C264C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C264C
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C264C-A2UR
Manufacturer:
INTERSIL
Quantity:
1 670
Part Number:
AT32UC3C264C-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- Current page: 165 of 377
- Download datasheet (5Mb)
32000D–04/2011
EOR – Logical Exclusive OR with optional logical shift
Architecture revision:
Architecture revision1 and higher.
Description
Performs a bitwise logical Exclusive-OR between the specified registers and stores the result in
the destination register.
Operation:
I.
II.
III.
Syntax:
I.
II.
III.
Operands:
I.
II, III.
Status Flags
Opcode:
15
31
0
1
15
0
Rd ← Rd ⊕ Rs;
Rd ← Rx ⊕ (Ry << sa5);
Rd ← Rx ⊕ (Ry >> sa5);
eor
eor
eor
{d, s} ∈ {0, 1, …, 15}
{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
Q:
V:
N:
Z:
C:
Format I:
Format II:
0
1
0
13
29
0
1
1
Rd, Rs
Rd, Rx, Ry << sa
Rd, Rx, Ry >> sa
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
Not affected
12
28
0
0
Rx
Rs
0
9
9
25
0
8
8
0
24
1
0
1
sa5
1
1
0
1
4
4
1
20
0
3
3
19
Ry
Rd
Rd
AVR32
0
0
16
165
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