AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 180

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.7.16
Name:
Access Type:
Offset:
Reset Value:
• AWIRE: aWire Reset
• JTAG: JTAG Reset
• OCDRST: OCD Reset
• SLEEP: Sleep Reset
• WDT: Watchdog Reset
• EXT: External Reset Pin
• BOD: Brown-out Reset
• POR: Power-on Reset
32145A–12/2011
31
23
15
7
-
-
-
-
This bit is set when the last reset was caused by the aWire.
This bit is set when the last reset was caused by the JTAG.
This bit is set when the last reset was due to the RES bit in the OCD Development Control register having been written to one.
This bit is set when the last reset was due to the device waking up from the Shutdown sleep mode.
This bit is set when the last reset was due to a watchdog time-out.
This bit is set when the last reset was due to the RESET_N pin being pulled low.
This bit is set when the last reset was due to the core supply voltage being lower than the brown-out threshold level.
This bit is set when the last reset was due to the core supply voltage VDDCORE being lower than the power-on threshold level
(the reset is generated by the POR18 detector), or the internal regulator supply voltage being lower than the regulator power-on
threshold level (generated by the POR33 detector), or the internal regulator supply voltage being lower than the minimum
required input voltage (generated by the 3.3V supply monitor SM33).
Reset Cause Register
SLEEP
30
22
14
RCAUSE
Read-only
0x180
Latest Reset Source
6
-
-
-
29
21
13
5
-
-
-
-
AWIRE
28
20
12
4
-
-
-
WDT
27
19
11
3
-
-
-
EXT
26
18
10
2
-
-
AT32UC3L0128/256
JTAG
BOD
25
17
9
1
-
-
OCDRST
POR
24
16
8
0
-
-
180