AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 148

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

148
AVR32
CACHE – Perform Cache control operation
Architecture revision:
Architecture revision1 and higher.
Description
Control cache operation.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Issue a command to the cache
cache Rp[disp], Op5
disp ∈ {-1024, -1023, ..., 1023}
p ∈ {0, 1, …, 15}
Q:
V:
N:
Z:
C:
00
01
10
11
000
001
010
011
100
101
110
111
Op[4:3]
Op[2:0]
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Data Cache or unified cache
Secondary Cache
Implementation definedk
Implementation defined
Implementation defined
Implementation defined
Implementation defined
Implementation defined
Implementation defined
Implementation defined
Instruction Cache
Tertiary Cache
Semantic
Semantic
32000D–04/2011