AT83C5136 Atmel Corporation, AT83C5136 Datasheet
AT83C5136
Specifications of AT83C5136
Related parts for AT83C5136
AT83C5136 Summary of contents
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... EEPROM only available on MLF48 1. Description AT83C5134/35/36 are high performance ROM versions of the 80C51 single-chip 8-bit microcontrollers with full speed USB functions. AT83C5134/35 is pin compatible with AT89C5130A 16- Kbytes In-System Programmable Flash microcontrollers. 8-bit Microcontroller with Full Speed USB Device AT83C5134 AT83C5135 AT83C5136 ...
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... This allows to use AT89C5130A for development, pre-production and flexibility, while using AT83C5134/35 for cost reduction in mass production. Similarly AT83C5136 is pin compatible with AT89C5131A 32-Kbytes Flash microcontroller. AT83C5134/35/36 features a full-speed USB module compatible with the USB specifications Version 2.0. This module integrates the USB transceivers and the Serial Interface Engine (SIE) with Digital Phase Locked Loop and 48 MHz clock recovery ...
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Block Diagram (2) XTAL1 XTAL2 EUART ALE PSEN CPU EA (2) Timer 0 RD Timer 1 (2) WR (2) (2) * EEPROM only available in MLF48 Notes: 1. Alternate function of Port 1 2. Alternate function of Port 3 ...
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Pinout Description 4.1 Pinout Figure 4-1. AT83C5134/35/36 4 AT83C5134/35/36 64-pin VQFP Pinout P2.3/A11 3 P2.4/A12 4 P2.5/A13 5 XTAL2 6 XTAL1 7 P2.6/A14 8 ...
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Figure 4-2. Figure 4-3. 7683C–USB–11/07 AT83C5134/35/36 48-pin MLF Pinout P4.1/SDA 1 P2.3/A11 2 P2.4/A12 3 4 P2.5/A13 5 XTAL2 6 XTAL1 P2.6/A14 7 MLF48 P2.7/A15 8 9 VDD ...
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Figure 4-4. 4.2 Signals All the AT83C5134/35/36 signals are detailed by functionality on Table 4-1 through Table 4-12. Table 4-1. Signal Name KIN[7:0) Table 4-2. Signal Name ECI CEX[4:0] AT83C5134/35/36 6 AT83C5134/35/36 32-pin QFN Pinout ...
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Table 4-3. Signal Name RxD TxD Table 4-4. Signal Name INT0 INT1 T2EX Table 4-5. Signal Name LED[3:0] 7683C–USB–11/07 Serial I/O Signal Description Type Description Serial Input I The serial input for Extended UART. This I/O is ...
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Table 4-6. Signal Name SCL SDA Table 4-7. Signal Name SS MISO SCK MOSI Table 4-8. Signal Name P0[7:0] P1[7:0] P2[7:0] AT83C5134/35/36 8 TWI Signal Description Type Description SCL: TWI Serial Clock I/O SCL output the serial clock to slave ...
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Signal Name P3[7:0] P4[1:0] Table 4-9. Signal Name XTAL1 XTAL2 PLLF Table 4-10. Signal Name D+ D- VREF Table 4-11. Signal Name AD[7:0] A[15:8] 7683C–USB–11/07 Type Description Port 3 I 8-bit bidirectional I/O port with internal pull-ups. ...
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Signal Name RD WR RST ALE PSEN EA Table 4-12. Signal Name AVSS AVDD VSS VDD VREF AT83C5134/35/36 10 Type Description Read Signal Read signal asserted during external data memory read operation. I/O Control input for slave port read access ...
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Typical Application 5.1 Recommended External components All the external components described in the figure below must be implemented as close as pos- sible from the microcontroller package. The following figure represents the typical wiring schematic. Figure 5-1. Typical Application ...
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PCB Recommandations Figure 5-2. Note: Figure 5-3. AT83C5134/35/36 12 USB Pads Components must be close to the microcontroller VRef possible, isolate D+ and D- signals from other signals with ground wires No sharp angle in above ...
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Clock Controller 6.1 Introduction The AT83C5134/35/36 clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller. The AT83C5134/35/36 X1 ...
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In order to optimize the power consumption, the oscillator inverter is inactive when the PLL out- put is not selected for the USB device. Figure 6-2. 6.3 PLL 6.3.1 PLL Description The AT83C5134/35/36 PLL is used to generate internal high ...
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Figure 6-4. The typical values are 560 Ω 820 pf 150 pF. 6.3.2 PLL Programming The PLL is programmed using the flow shown in Figure 6-5. As soon as clock generation is enabled user ...
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Oscillator Frequency 6.4 Registers Table 6-2. 7 TWIX2 Bit Number Reset Value = 0000 0000b AT83C5134/35/36 16 R+1 32 MHz 3 40 MHz 12 CKCON0 (S:8Fh) Clock Control Register ...
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Table 6- Bit Number 7-1 0 Reset Value = 0000 0000b Table 6- Bit Number 7 Reset Value = 0000 0000b Table 6- Bit Number 7-4 3-0 Reset Value = 0000 ...
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SFR Mapping The Special Function Registers (SFRs) of the AT83C5134/35/36 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4 • Timer registers: T2CON, T2MOD, ...
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The table below shows all SFRs with their address and their reset value. Table 7-1. SFR Descriptions Bit Addressable 0/8 1/9 CH UEPINT F8h 0000 0000 0000 0000 LEDCON B F0h 0000 0000 0000 0000 CL E8h 0000 0000 ACC ...
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Table 7-2. Mnemonic ACC B PSW SP DPL DPH Table 7-3. Mnemonic Table 7-4. Timer SFR’s Mnemonic Add Name TH0 8Ch Timer/Counter 0 High byte TL0 8Ah Timer/Counter 0 Low byte TH1 8Dh Timer/Counter 1 ...
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Table 7-4. Timer SFR’s (Continued) Mnemonic Add Name Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte WDTRST A6h WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program Table 7-5. Serial I/O Port SFR’s Mnemonic Add ...
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Table 7-7. PCA SFR’s Mnemo- nic Add Name CCAP0 PCA Compare Capture Module CCAP1 PCA Compare Capture Module 1 FAh H H FBh CCAP2 PCA Compare Capture Module 2 FCh H H FDh CCAP3 PCA Compare Capture ...
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Table 7-10. Keyboard SFRs Mnemonic Add Name Keyboard Level KBLS 9Ch Selector Register Table 7-11. TWI SFRs Mnemonic Add Name Synchronous Serial SSCON 93h Control Synchronous Serial SSCS 94h Control-Status Synchronous Serial SSDAT 95h Data Synchronous Serial SSADR 96h Address ...
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Table 7-13. USB SFR’s Mnemonic Add Name USB Byte Counter Low UBYCTLX E2h (EP X) USB Byte Counter High UBYCTHX E3h (EP X) USB Frame Number UFNUML BAh Low USB Frame Number UFNUMH BBh High Table 7-14. Other SFR’s Mnemonic ...
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... Fetching code constant from this location does not affect Ports 0 and 2. External Code Memory Interface Structure AT89C5131 P2 ALE AD7:0 P0 PSEN AT83C5134/35/36 FFFFh 32 Kbytes External Code 8000h 7FFFh 32 Kbytes ROM 0000h AT83C5136 Flash EPROM A15:8 A15:8 Latch A7:0 A7:0 D7 ...
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Table 8-1. Signal Name A15:8 AD7:0 ALE PSEN 8.1.2 External Bus Cycles This section describes the bus cycles the AT83C5134/35/36 executes to fetch code (see Figure 8-3) in the external program/code memory. External memory cycle takes 6 CPU clock periods. ...
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AT89C5131 ROM 9.1 ROM Structure The AT89C5131 ROM memory is divided in two different arrays: • the code array: 16-32 Kbytes. • the configuration byte:1 byte. 9.1.1 Hardware Configuration Byte The configuration byte sets the starting microcontroller options and ...
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Program ROM lock Bits The lock bits when programmed according to Table 9-2 will provide different level of protection for the on-chip code and data. Table 9-2. Program Lock Bits Security level unprogrammed P: programmed AT83C5134/35/36 ...
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Stacked EEPROM 10.1 Overview The AT83C5134/35/36 features a stacked 2-wire serial data EEPROM. The data EEPROM allows to save from 512 Byte for AT24C04 version Kbytes for AT24C256 version. The EEPROM is internally connected to the ...
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On-chip Expanded RAM (ERAM) The AT83C5134/35/36 provides additional Bytes of random access memory (RAM) space for increased data parameters handling and high level language usage. AT83C5134/35/36 devices have an expanded RAM in the external data space; maximum size and ...
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Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: ...
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Bit Number Reset Value = 0X0X 1100b Not bit addressable AT83C5134/35/36 32 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit XRS1 ERAM Size XRS1XRS0 ERAM ...
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Timer 2 The Timer 2 in the AT83C5134/35/36 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2 controlled by T2CON (Table 12-1) ...
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Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH 12.2 Programmable Clock Output In the Clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 12-2). The input clock increments TL2 at frequency F ...
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It is possible to use Timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the RCAP2H and ...
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Table 12-1. 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT83C5134/35/36 36 T2CON Register T2CON - Timer 2 Control Register (C8h EXF2 RCLK TCLK Bit Mnemonic ...
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Table 12- Bit Number Reset Value = xxxx xx00b Not bit addressable 7683C–USB–11/07 T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit ...
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Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time ...
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Figure 13-1. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle Table 13-1. 7 CIDL Bit Number 7683C–USB–11/07 CH CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 ...
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Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA (See Figure 13-1 and Table 13-1). • The CIDL bit allows the PCA to stop during idle mode. • The WDTE ...
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Bit Number 1 0 Reset Value = 000X 0000b Not bit addressable The watchdog timer function is implemented in module 4 (See Figure 13-4). The PCA interrupt system is shown in Figure 13-2. Figure 13-2. PCA Interrupt System PCA Timer/Counter ...
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The ECCF bit (CCAPMn.0 where depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. ...
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Bit Number 1 0 Reset Value = X000 0000b Not bit addressable Table 13-4. ECOMn There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL ...
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Table 13-5. CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh) CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register ...
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Table 13- PCA Counter Register Low (0E9h Bit Number Reset Value = 0000 0000b Not bit addressable 13.1 PCA Capture Mode To use one of the PCA modules in the capture mode either ...
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Figure 13-4. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 Note: Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match ...
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Figure 13-5. PCA High-speed Output Mode Write to Reset CCAPnL Write to CCAPnH 0 1 Enable Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match could happen. Once ECOM ...
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Figure 13-6. PCA PWM Mode 13.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, ...
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Serial I/O Port The serial I/O port in the AT83C5134/35/36 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter (UART) ...
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Figure 14-3. UART Timings in Modes 2 and 3 14.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition ...
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Slave C:SADDR1111 0011b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t care bit; for slaves B and C, bit communicate ...
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SADEN - Slave Address Mask Register (B9h) 7 Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h) 7 Reset Value = 0000 0000b Not bit addressable 14.3 Baud Rate Selection for UART for Mode 1 ...
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Baud Rate Selection Table for UART TCLK RCLK (T2CON) (T2CON 14.3.2 Internal Baud Rate Generator (BRG) When the internal Baud Rate ...
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Bit Number Reset Value = 0000 0000b Bit addressable AT83C5134/35/36 54 Bit Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop ...
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Example of computed value when SMOD1 = 1, SPD = 1 Baud Rates 115200 Example of computed value when SMOD1 = 0, SPD = 0 Baud Rates The baud rate generator can be used ...
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BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) 7 – Reset Value = 0000 0000b Table 14-2. T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number ...
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Table 14-3. PCON - Power Control Register (87h) 7 SMOD1 Bit Number Reset Value = 00x1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on ...
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Table 14-4. BDRCON - Baud Rate Control Register (9Bh Bit Number Reset Value = xxx0 0000b Not bit addressable AT83C5134/35/36 58 BDRCON Register BRR Bit ...
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Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data ...
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Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE ...
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Interrupt System 16.1 Overview The AT83C5134/35/36 has a total of 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the ...
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High register each combination. 16.2 Registers The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors addresses are the same ...
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Table 16-2. IEN0 - Interrupt Enable Register (A8h Bit Number Reset Value = 0000 0000b Bit addressable 7683C–USB–11/07 IEN0 Register ET2 ES Bit Mnemonic Description Enable ...
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Table 16-3. IPL0 - Interrupt Priority Register (B8h Bit Number Reset Value = x000 0000b Bit addressable AT83C5134/35/36 64 IPL0 Register PPCL PT2L PSL Bit Mnemonic Description ...
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Table 16-4. IPH0 - Interrupt Priority High Register (B7h Bit Number Reset Value = x000 0000b Not bit addressable 7683C–USB–11/07 IPH0 Register PPCH PT2H PSH Bit Mnemonic ...
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Table 16-5. IEN1 - Interrupt Enable Register (B1h Bit Number Reset Value = x0xx x000b Not bit addressable AT83C5134/35/36 66 IEN1 Register EUSB - - Bit Mnemonic ...
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Table 16-6. IPL1 - Interrupt Priority Register (B2h Bit Number Reset Value = X0XX X000b Not bit addressable 7683C–USB–11/07 IPL1 Register PUSBL - - Bit Mnemonic Description ...
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Table 16-7. IPH1 - Interrupt Priority High Register (B3h Bit Number Reset Value = X0XX X000b Not bit addressable AT83C5134/35/36 68 IPH1 Register PUSBH - - Bit ...
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Interrupt Sources and Vector Addresses Table 16-8. Number 7683C–USB–11/07 Vector Table Polling Interrupt Priority Source 0 0 Reset 1 1 INT0 2 2 Timer INT1 4 4 Timer UART 6 7 Timer 2 ...
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Keyboard Interface 17.1 Introduction The AT83C5134/35/36 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are ...
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Power Reduction Mode P1 inputs allow exit from idle and power down modes as detailed in section “Power-down Mode”. 17.3 Registers Table 17-1. KBF - Keyboard Flag Register (9Eh) 7 KBF7 Bit Number ...
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Table 17-2. KBE - Keyboard Input Enable Register (9Dh) 7 KBE7 Bit Number Reset Value = 0000 0000b AT83C5134/35/36 72 KBE Register KBE6 KBE5 KBE4 Bit Mnemonic Description Keyboard ...
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Table 17-3. KBLS-Keyboard Level Selector Register (9Ch) 7 KBLS7 Bit Number Reset Value = 0000 0000b 7683C–USB–11/07 KBLS Register KBLS6 KBLS5 KBLS4 Bit Mnemonic Description Keyboard line 7 Level ...
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Programmable LED AT83C5134/35/36 have programmable LED current sources, configured by the register LEDCON. Table 18-1. LEDCON (S:F1h) LED Control Register 7 Bit Number 7:6 5:4 3:2 1:0 Reset Value = 00h AT83C5134/35/36 74 LEDCON Register 6 ...
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Serial Peripheral Interface (SPI) The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communica- tion between the MCU and peripheral devices, including other MCUs. 19.1 Features Features of the SPI module include the following: • Full-duplex, three-wire synchronous ...
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SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines driven by the Master for eight clock cycles which allows to exchange ...
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Functional Description Figure 19-2 Figure 19-2. SPI Module Block Diagram 19.3.1 Operating Modes The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI module ...
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Figure 19-3. Full-duplex Master/Slave Interconnection 19.3.1.1 Master Mode The SPI operates in Master mode when the Master bit, MSTR Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the ...
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Figure 19-4. Data Transmission Format (CPHA = 0) SCK cycle number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture point Figure 19-5. Data Transmission Format (CPHA = 1) ...
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Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a ...
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Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. Figure 19-7 gives a logical view of ...
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Bit Number Reset Value = 0001 0100b Not bit addressable 19.3.5.2 Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • Inconsistent ...
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Bit Number Reset Value = 00X0 XXXXb Not Bit addressable 19.3.5.3 Serial Peripheral Data Register (SPDAT) The Serial Peripheral Data Register ter. A write to SPDAT places data directly into the shift register. No transmit ...
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Two Wire Interface ( This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial com- munication standard designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two ...
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Figure 20-2. Block Diagram Input Filter SDA Output Stage Input Filter SCL Output Stage 7683C–USB–11/07 Address Register SSADR Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register SSCON Status ...
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Description The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON; ter (SSDAT; 12) and the Synchronous Serial Address register (SSADR SSCON is used to enable the TWI ...
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R : Read bit (high level at SDA Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In ...
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The serial interrupt flag SI must then be cleared before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, ...
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Slave Transmitter Mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 20-7). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the ...
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CR2 CR1 CR0 Figure 20-4. Format and State in the Master Transmitter Mode Successfull S SLA transmission to a slave receiver 08h Next transfer started with a repeated ...
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Table 20-5. Status in Master Transmitter Mode Status Status of the Two- Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT A START condition has 08h Write SLA+W been transmitted Write SLA+W A repeated START 10h condition has been ...
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Figure 20-5. Format and State in the Master Receiver Mode Successfull transmission S SLA to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or ...
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Table 20-6. Status in Master Receiver Mode Status Status of the Two- Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT A START condition has 08h Write SLA+R been transmitted Write SLA+R A repeated START 10h condition has been ...
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Figure 20-6. Format and State in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave ...
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Table 20-7. Status in Slave Receiver Mode Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Own SLA+W has been 60h received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+W has been 68h received; ...
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Table 20-7. Status in Slave Receiver Mode (Continued) Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Previously addressed with general call; data has been 98h received; NOT ACK has been returned A STOP condition or repeated START ...
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Figure 20-7. Format and State in the Slave Transmitter Mode Reception of the S own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave ...
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Table 20-8. Status in Slave Transmitter Mode (Continued) Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Data byte in SSDAT has been C0h transmitted; NOT ACK has been received Last data byte in SSDAT has C8h been ...
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Registers Table 20-10. SSCON Register SSCON - Synchronous Serial Control Register (93h) 7 CR2 Bit Number Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write) SD7 7 Bit Number 7 ...
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Bit Number 1 0 Table 20-12. SSCS (094h) Read - Synchronous Serial Control and Status Register 7 SC4 Bit Number Table 20-13. SSADR (096h) - Synchronous Serial Address Register (read/write ...
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USB Controller . 21.1 Description The USB device controller provides the hardware that the AT89C5131 needs to interface a USB link to a data flow stored in a double port memory (DPRAM). The USB controller requires a 48 MHz ...
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Address checking. • Clock generation (via DPLL). Figure 21-2. SIE Block Diagram End of Packet Detection Start of Packet Detection D+ D- Clk48 (48 MHz) 21.1.2 Function Interface Unit (FIU) The Function Interface Unit provides the interface between the ...
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Figure 21-3. UFI Block Diagram FIU DPLL SIE Figure 21-4. Minimum Intervention from the USB Device Firmware OUT Transactions: HOST OUT DATA0 (n bytes) UFI C51 IN Transactions: HOST IN UFI NACK C51 Endpoint FIFO write 21.2 Configuration 21.2.1 General ...
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Set configuration The CONFG bit in the USBCON register has to be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit has to be cleared. 21.2.2 Endpoint Configuration • Selection of an Endpoint The endpoint register ...
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The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type. • Endpoint direction configuration For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of the UEPCONX register with the ...
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Figure 21-6. Endpoint FIFO Configuration UEPSTA0 Endpoint 0 UEPSTA5 Endpoint 5 21.3.2 Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the ...
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Bulk/Interrupt OUT Transactions in Standard Mode Figure 21-7. Bulk/Interrupt OUT transactions in Standard Mode An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on ...
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Bulk/Interrupt OUT Transactions in Ping-pong Mode Figure 21-8. Bulk/Interrupt OUT Transactions in Ping-pong Mode An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on ...
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A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released by the firmware. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be ...
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Bulk/Interrupt IN Transactions in Ping-pong Mode Figure 21-10. Bulk/Interrupt IN Transactions in Ping-pong Mode An endpoint will be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware will fill the FIFO bank 0 ...
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The firmware will never write more bytes than supported by the endpoint FIFO. 21.5 Control Transactions 21.5.1 Setup Stage The DIR bit in the UEPSTAX register will Receiving Setup packets is the same as receiving Bulk Out ...
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Isochronous Transactions 21.6.1 Isochronous OUT Transactions in Standard Mode An endpoint will be first enabled and configured before being able to receive Isochronous packets. When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by ...
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The firmware has to clear one of these two bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank. If the Host sends more bytes than supported by the endpoint ...
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STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the ...
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The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Clear suspend interrupt bit in USBINT (required to allow the USB pads to enter power down mode). 2. Enable USB resume interrupt. ...
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Upstream Resume A USB device can be allowed by the Host to send an upstream resume for Remote Wake Up purpose. When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware will set to 1 the RMWUPE bit ...
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Detach Simulation In order to be re-enumerated by the Host, the AT83C5134/35/36 has the possibility to simulate a DETACH - ATTACH of the USB bus. The V REF up as shown in set the USBCON register. ...
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Table 21-2. 21.10.2 USB Interrupt Control System As shown in Figure 21-16, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data (see when the Host accept a In packet. • RXOUTB0: Received Out Data Bank 0 (see ...
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Figure 21-16. USB Interrupt Control Block Diagram Endpoint 0..5) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.0 7683C–USB–11/07 EPXINT ...
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USB Registers Table 21-3. 7 USBE Bit Number Reset Value = 00h AT83C5134/35/36 120 USBCON Register USBCON (S:BCh) USB Global Control Register SUSPCLK SDRMWUP DETACH Bit Mnemonic Description ...
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Table 21- Bit Number 7 Reset Value = 00h 7683C–USB–11/07 USBINT Register USBINT (S:BDh) USB Global Interrupt Register WUPCPU EORINT Bit Mnemonic Description Reserved - The value read ...
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Table 21- Bit Number 7 Reset Value = 10h AT83C5134/35/36 122 USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register EWUPCPU EEORINT Bit Mnemonic Description Reserved - The ...
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Table 21-6. 7 FEN Bit Number 7 6-0 Reset Value = 80h Table 21- Bit Number 7-4 3-0 Reset Value = 00h 7683C–USB–11/07 USBADDR Register USBADDR (S:C6h) USB Address Register UADD6 UADD5 UADD4 Bit Mnemonic ...
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Table 21-8. 7 EPEN Bit Number 1-0 Note: Reset Value = 80h when UEPNUM = 0 (default Control Endpoint) Reset Value = 00h otherwise for all other endpoints AT83C5134/35/36 124 UEPCONX Register UEPCONX (S:D4h) ...
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Table 21-9. UEPSTAX (S:CEh) USB Endpoint X Status Register 7 6 DIR RXOUTB1 Bit Bit Number Mnemonic Description Control Endpoint Direction This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h) ...
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Table 21-10. UEPDATX Register UEPDATX (S:CFh) USB FIFO Data Endpoint FDAT7 FDAT6 Bit Number Bit Mnemonic Description Endpoint X FIFO data FDAT [7:0] Data byte to be written to FIFO or data byte to ...
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Table 21-13. UEPRST Register 7 - Bit Number Reset Value = 00h 7683C–USB–11/07 UEPRST (S:D5h) USB Endpoint FIFO Reset Register EP5RST EP4RST Bit Mnemonic Description Reserved - The ...
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Table 21-14. UEPINT Register 7 - Bit Number Reset Value = 00h AT83C5134/35/36 128 UEPINT (S:F8h read-only) USB Endpoint Interrupt Register EP5INT EP4INT Bit Mnemonic Description Reserved - ...
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Table 21-15. UEPIEN Register 7 - Bit Number Reset Value = 00h 7683C–USB–11/07 UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register EP5INTE EP4INTE Bit Mnemonic Description Reserved - The ...
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Table 21-16. UFNUMH Register 7 - Bit Number 2-0 Reset Value = 00h Table 21-17. UFNUML Register 7 FNUM7 Bit Number Reset Value = 00h AT83C5134/35/36 130 UFNUMH (S:BBh, read-only) USB Frame Number High ...
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Reset 22.1 Introduction The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 22-1. Reset schematic 22.2 Reset Input The Reset input can be used to force a reset pulse longer than the internal reset ...
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Figure 22-3. Recommended Reset Output Schematic AT83C5134/35/36 132 VDD RST RST AT89C5131A-M 1K VSS + VSS To other on-board circuitry 7683C–USB–11/07 ...
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Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an ...
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Figure 23-2. Power Fail Detect Vcc Reset Vcc When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL ...
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Power Management 24.1 Idle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the ...
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Figure 24-1. Power-down Exit Waveform INT0 INT1 XTAL Active Phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter- rupt does no affect the SFRs. Exit from power-down by either reset or external interrupt ...
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Registers Table 24-2. PCON (S:87h) Power Control Register 7 SMOD1 Bit Number Reset Value = 10h 7683C–USB–11/07 PCON Register SMOD0 - POF Bit Mnemonic Description Serial Port Mode ...
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Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is ...
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Table 25- Bit Number Reset value = XXXX X000 25.2 WDT During Power-down and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power- ...
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Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with exter- nal program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...
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Electrical Characteristics 27.1 Absolute Maximum Ratings Ambient Temperature Under Bias industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage on V from V ......................................-0. Voltage on Any Pin from ...
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Symbol Parameter V Power Fail Low Level Threshold PFDM Power fail hysteresis V PFDP Notes: 1. Operating I is measured with all output pins disconnected; XTAL1 driven with 0.5V 0.5V; XTAL2 ...
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Figure 27-2. I Figure 27-3. I Figure 27-4. Clock Signal Waveform for I 27.2.1 LED’s Table 27-1. LED Outputs DC Parameters Symbol Parameter I Output Low Current, P3.6 and P3.7 LED modes OL Note -20°C to +50°C, ...
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USB DC Parameters 27.4 AC Parameters 27.4.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name ...
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Example 170 ns CCIV 27.4.2 External Program Memory Characteristics Table 27-2. Table 27-3. AT83C5134/35/36 146 and 20 MHz, Standard clock. LLIV Symbol Description Symbol Parameter ...
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Table 27-4. 27.4.3 External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 7683C–USB–11/07 AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max LLIV ...
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External Data Memory Characteristics Table 27-5. Table 27-6. AT83C5134/35/36 148 Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data ...
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Table 27-7. 27.4.5 External Data Memory Write Cycle ALE PSEN WR PORT 0 PORT 2 7683C–USB–11/07 AC Parameters for a Variable Clock Standard Symbol Type Clock T Min RLRH T Min WLWH ...
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External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 27.4.7 Serial Port Timing - Shift Register Mode Table 27-8. Table 27-9. Table 27-10. AC Parameters for a Variable Clock AT83C5134/35/36 150 T LLDV ...
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Shift Register Timing Waveform INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 27.4.9 External Clock Drive Characteristics (XTAL1) Table 27-11. AC Parameters 27.4.10 External Clock Drive Waveforms 27.4.11 AC Testing Input/Output Waveforms AC ...
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Clock Waveforms Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE ...
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Table 27-12. Memory AC Timing 27.5 USB AC Parameters V CRS Differential Data Lines Table 27-13. USB AC Parameters 27.6 SPI Interface AC Parameters 27.6.0.1 Definition of Symbols Table 27-14. SPI Interface Timing Symbol Definitions 7683C–USB–11/07 VDD = 3.3V ± ...
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Timings Test conditions: capacitive load on all pins= 50 pF. Table 27-15. SPI Interface Master AC Timing V = 2 CHCH T CHCX T CLCX T SLCH T IVCL T CLIX T CLOV, ...
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Waveforms Figure 27-5. SPI Slave Waveforms (CPHA= 0) (input) (CPOL= 0) (input) (CPOL= 1) (input) MISO (output) MOSI (input) Note: Figure 27-6. SPI Slave Waveforms (CPHA= 1) (input) SCK (CPOL= 0) (input) SCK (CPOL= 1) (input) MISO (output) MOSI ...
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Figure 27-7. SPI Master Waveforms (SSCPHA (output) SCK (CPOL= 0) (output) SCK (CPOL= 1) (output) MOSI (input) MISO (output) Note: Figure 27-8. SPI Master Waveforms (SSCPHA (output) SCK (CPOL= 0) (output) SCK (CPOL= 1) (output) MOSI ...
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... Ordering Information Table Possible Order Entries Part Number AT83C5134xxx-PNTUL AT83C5135xxx-PNTUL AT83C5136xxx-PNTUL AT83C5136xxx-PLTUL AT83C5136xxx-TISUL AT83C5136-RDTUL AT83C5136xxx-DDW 32KB with 512-byte of AT83EC5136xxx-PNTUL 32KB with 32-kbyte of AT83EI5136xxx-PNTUL 7683C–USB–11/07 Memory Size Supply Voltage 8KB 2.7 to 3.6V 16KB 2.7 to 3.6V 32KB 2.7 to 3.6V 32KB 2.7 to 3.6V 32KB 2.7 to 3.6V 32 2.7 to 3.6V 32KB 2.7 to 3.6V 2.7 to 3.6V EEPROM 2.7 to 3.6V EEPROM AT83C5134/35/36 ...
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Packaging Information 29.1 64-lead VQFP AT83C5134/35/36 158 7683C–USB–11/07 ...
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MLF 7683C–USB–11/07 AT83C5134/35/36 159 ...
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AT83C5134/35/36 160 7683C–USB–11/07 ...
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SO 7683C–USB–11/07 AT83C5134/35/36 161 ...
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QFN32 AT83C5134/35/36 162 7683C–USB–11/07 ...
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Document Revision History 30.1 Changes from Rev A. to Rev Added QFN32 package. 30.2 Changes from Rev B. to Rev Updated package drawings. 7683C–USB–11/07 AT83C5134/35/36 163 ...
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Features .................................................................................................... 1 2 Description ............................................................................................... 1 3 Block Diagram .......................................................................................... 3 4 Pinout Description ................................................................................... 4 5 Typical Application ................................................................................ 11 6 Clock Controller ..................................................................................... 13 7 SFR Mapping .......................................................................................... 18 8 Program/Code Memory ......................................................................... 25 9 AT89C5131 ...
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Serial I/O Port ......................................................................................... 49 15 Dual Data Pointer Register.................................................................... 59 16 Interrupt System .................................................................................... 61 17 Keyboard Interface ................................................................................ 70 18 Programmable LED................................................................................ 74 19 Serial Peripheral Interface (SPI) ........................................................... 75 20 Two Wire Interface (TWI) ....................................................................... 84 ...
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Reset ..................................................................................................... 131 23 Power Monitor ...................................................................................... 133 24 Power Management ............................................................................. 135 25 Hardware Watchdog Timer ................................................................. 138 26 Reduced EMI Mode .............................................................................. 141 27 Electrical Characteristics .................................................................... 142 28 Ordering Information ........................................................................... 157 29 Packaging Information ........................................................................ ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...