AT89C51ED2 Atmel Corporation, AT89C51ED2 Datasheet

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AT89C51ED2

Manufacturer Part Number
AT89C51ED2
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C51ED2

Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Sram (kbytes)
2
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART
Watchdog
Yes

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Active Errata List
Errata History
Errata Descriptions
1. During UART Reception, Clearing REN May Generate Unexpected IT
2. Timer 2 – Baud Rate Generator
3. C51 Core
4. PCA
5. Timer0/1
Lot Number
All
During UART Reception, Clearing REN May Generate Unexpected IT
Timer 2 – Baud Rate Generator – Long Start Time
C51 Core – Bad Exit of Power-down in X2 Mode
PCA
Timer0/1
Boot process - Upper 2Kbytes execution with BLJB=0
Flash/EEPROM - First Read after Load Disturbed
During UART reception, if the REN bit is cleared between start bit detection and
the end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine directly after CLR RI, and run the
Interrupt routine code only if REN is set.
When Timer 2 is used as a baud rate generator, TH2 is not loaded with RCAP2H
at the beginning, then UART is not operational before 10,000 machine cycles.
Workaround
Add the initialization of TH2 and TL2 in the initialization of Timer 2.
When exiting power-down mode by interrupt while CPU is in X2 mode, it leads to
bad execution of the first instruction run when CPU restarts.
Workaround
Set the CPU in X1 mode diretly before entering power-down mode.
When starting the microcontroller in X2 mode upon reset with the X2 fuse bit of
the HSB, the PCA may not work properly when configured with Timer 0 in X1
mode as clock input.
Workaround
Set the CPU in X2 mode by software by writing CKCON register at the begin of
the application.
When Timer0 is in X1 mode and Timer1 in X2 mode and vice versa, extra inter-
rupt may randomly occur for Timer0 or Timer1.
Workaround
Incorrect Behavior with CPU X2 Mode Bit of HSB
Incorrect behavior with CPU X2 mode bit of HSB
Extra Interrupt
Extra Interrupt
Bad Exit of Power-down in X2 Mode
Long Start Time
Errata List
1, 2, 3, 4, 5, 6, 7
80C51 MCUs
AT89C51RD2
AT89C51ED2
Errata Sheet
4257E–8051–08/07

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AT89C51ED2 Summary of contents

Page 1

... Extra Interrupt – When Timer0 mode and Timer1 in X2 mode and vice versa, extra inter- rupt may randomly occur for Timer0 or Timer1. Workaround Errata List Long Start Time – 80C51 MCUs AT89C51RD2 AT89C51ED2 Errata Sheet 4257E–8051–08/07 ...

Page 2

Use the same mode for the two timers.. 6. Boot Process - Upper 2Kbytes Execution with BLJB = 0 In case of Boot process with BLJB = 0 and BSB = 00, the User Application is executed but the program ...

Page 3

Active UART Bootloader Errata List • API program Data Byte - Incorrect Return Value • API program Data Page - Incorrect Return Value UART Bootloader Errata History Version Number 0.0 (1.0.0 displayed by FLIP) UART Bootloader Errata Description 1. API ...

Page 4

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. ©2007 Atmel Corporation. All rights reserved. Atmel tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...

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