AT89LP213 Atmel Corporation, AT89LP213 Datasheet
AT89LP213
Specifications of AT89LP213
Related parts for AT89LP213
AT89LP213 Summary of contents
Page 1
... MCS-51 instruction set. The AT89LP213/214 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc- tions to execute in 12 clock cycles. In the AT89LP213/214 CPU, instructions ® 51 Products ...
Page 2
... In addition, the timer/counters on the AT89LP213 may independently drive a pulse width modulation output. The I/O ports of the AT89LP213/214 can be independently configured in one of four operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode pro- vides just a pull-down ...
Page 3
... Pin Description Table 3-1. AT89LP213 Pin Description Pin Symbol Type Description I/O P1.5: User-configurable I/O Port 1 bit 5. I/O MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as 1 P1.5 slave, this pin is an input. I GPI5: General-purpose Interrupt input 5. I/O P1.7: User-configurable I/O Port 1 bit 7. I/O SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin ...
Page 4
... SS: SPI slave select input. I GPI4: General-purpose Interrupt input 4. I/O P1.6: User-configurable I/O Port 1 bit 6. I/O MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured 14 P1.6 as slave, this pin is an output. I GPI6: General-purpose Interrupt input 6. AT89LP213/214 4 See “External Reset” on page 16). 3538E–MICRO–11/10 ...
Page 5
... Block Diagram Figure 4-1. Figure 4-2. 3538E–MICRO–11/10 AT89LP213 Block Diagram Single Cycle 8051 CPU 2KB Flash 128 Bytes RAM Port 3 Configurable I/O Port 1 Configurable I/O General-purpose Interrupt AT89LP214 Block Diagram Single Cycle 8051 CPU 2KB Flash 128 Bytes RAM Port 3 Configurable I/O Port 1 Configurable I/O ...
Page 6
... Comparison to Standard 8051 The AT89LP213/214 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051 ...
Page 7
... Reset The RST pin of the AT89LP213/214 is active-low as compared with the active high reset in the standard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a minimum of two clock cycles, instead of 24 clock cycles recognized as a valid reset. ...
Page 8
... Data Memory The AT89LP213/214 contains 128 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. The 128 bytes of data memory may be accessed through both direct and indirect addressing of the lower 128 byte addresses. The 128 ...
Page 9
... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 7-1. AT89LP213/214 SFR Map and Reset Values 8 9 0F8H ...
Page 10
... Enhanced CPU The AT89LP213/214 uses an enhanced 8051 CPU that runs times the speed of stan- dard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...
Page 11
... All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K for the AT89LP213/214. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction, whereas LJMP 900H would not. ...
Page 12
... When using the crystal oscillator, P3.2 and P3.3 will have their inputs and outputs disabled. When using the crystal oscillator, XTAL2 should not be used to drive a board-level clock without a buffer. Figure 9-1. Note: AT89LP213/214 12 72. Clock Source Settings Clock Source Fuse 0 ...
Page 13
... Figure 9-2. 9.3 Internal RC Oscillator The AT89LP213/214 has an internal RC oscillator tuned to 8.0 MHz ±1.0% at 5.0V and 25° C. When enabled as the clock source, XTAL1 and XTAL2 may be used as P3.2 and P3.3 respec- tively. XTAL2 may also be configured to output a divided version of the system clock. The frequency of the oscillator may be adjusted by changing the RC Adjust Fuses. ...
Page 14
... During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP213/214 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset. ...
Page 15
... RST RST (RST Controlled Externally approximately 92 µs ± 5%. POR (Table 10-1). The start-up delay should be selected to provide enough settling and the selected clock source. The Start-Up Time fuses also control the length of CC AT89LP213/214 V POR (RST Tied RHD ...
Page 16
... SUT Fuse 1 10.2 Brown-out Reset The AT89LP213/214 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD is nominally 2.2V. The purpose of the BOD is to ensure that if V speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution ...
Page 17
... WDRST register. A software reset will set the SWRST bit in WDT- CON. See “Software Reset” on page 59 11. Power Saving Modes The AT89LP213/214 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. 11.1 Idle Mode Setting the IDL bit in PCON enters idle mode ...
Page 18
... CPU until after the timer has timed out. The time-out period is controlled by the Start-up Timer Fuses. (See a two clock cycle internal reset is generated when the internal clock restarts. Otherwise the device will remain in reset until RST is brought high. AT89LP213/214 18 t SUT Figure 11-3 ...
Page 19
... Idle Mode bit. Setting this bit activates Idle mode operation 12. Interrupts The AT89LP213/214 provides 7 interrupt sources: two external interrupts, two timer interrupts, a serial port interrupt, a general-purpose interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space ...
Page 20
... SPIF and the general-purpose interrupt flags in GPIF. These flags are only set by hardware and may only be cleared by software. Table 12-1. Interrupt System Reset External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port General-purpose Interrupt Analog Comparator AT89LP213/214 20 Interrupt Vector Addresses Source RST or POR or BOD IE0 TF0 IE1 TF1 SPIF GPIF CF ...
Page 21
... Figure 12-1. Minimum Interrupt Response Time Figure 12-2. Maximum Interrupt Response Time 3538E–MICRO–11/10 Figures 12-1 and 12-2. Clock Cycles 1 INT0 IE0 Ack. Instruction Cur. Instr. LCALL Clock Cycles 1 INT0 IE0 Instruction RETI AT89LP213/214 5 1st ISR Instr. 13 Ack. 4 Cyc. Instr. LCALL 1st ISR In 21 ...
Page 22
... Symbol Function PGP General-purpose Interrupt Priority Low PS Serial Port Interrupt Priority Low PT1 Timer 1 Interrupt Priority Low PX1 External Interrupt 1 Priority Low PT0 Timer 0 Interrupt Priority Low PX0 External Interrupt 0 Priority Low AT89LP213/214 22 EGP ES ET1 PGP PS PT1 Reset Value = 0000 0000B ...
Page 23
... Timer 0 Interrupt Priority High PX0H External Interrupt 0 Priority High 13. I/O Ports The AT89LP213/214 can be configured for between 9 and 12 I/O pins. The exact number of I/O pins available depends on the clock and reset options as shown in 5V tolerant as inputs, that is they can be pulled up or driven to 5.5V even when operating at a lower V lup is required to convert outputs to CMOS levels ...
Page 24
... Port Configuration All port pins on the AT89LP213/214 may be configured to one of four modes: quasi-bidirectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may be assigned in software on a pin-by-pin basis as shown in Fuse determines the default state of the port pins. When the fuse is enabled, all port pins default to input-only mode after reset, with the exception of P1 ...
Page 25
... Data Figure 13-4.The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Figure 13-3). Open-drain pins can be safely pulled high to 5.5V even when levels; however, the input threshold of the Schmitt trigger will be set by CC level and must be taken into consideration. AT89LP213/214 Very Strong ...
Page 26
... Port 1 Analog Functions The AT89LP213/214 incorporates an analog comparator. In order to give the best analog perfor- mance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as described in inputs on P1 ...
Page 27
... Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP213/214 share functionality with the various I/Os needed for the peripheral units. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “ ...
Page 28
... P3.6 14. Enhanced Timer/Counters The AT89LP213/214 has two 16-bit Timer/Counter registers: Timer 0 and Timer Timer, the register increase every clock cycle by default. Thus, the register counts clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. ...
Page 29
... Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count Mode 0: Time-out Period RH1/RL1 are not required by Timer 1 during Mode 0 and may be used as temporary storage registers. OSC ÷TPS C C Pin Control TR1 GATE Figure AT89LP213/214 PSC0 1 + × 256 2 × ( ------------------------------------------------------ - = TPS + Oscillator Frequency ...
Page 30
... Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Figure 14-3. Timer/Counter 1 Mode 2: 8-bit Auto-reload Note: AT89LP213/214 30 Figure Mode 1: Time-out Period ÷TPS OSC ...
Page 31
... Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP213/214 can appear to have three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
Page 32
... Timer SFR TCON TMOD TL0 TL1 TH0 TH1 TCONB RL0 RL1 RH0 RH1 AT89LP213/214 GATE Mode Operating Mode 0 Variable 9 - 16-bit Timer mode. 8-bit Timer/Counter THx with TLx 8-bit prescaler. 1 16-bit auto-reload mode. 16-bit Timer/Counters THx and TLx are cascaded; there is no prescaler. ...
Page 33
... PSC00 14.5 Pulse Width Modulation On the AT89LP213, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetri- cal (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the timer's input pin T1. Therefore, C/T must be set to “0” when in PWM mode. and the T0 (P3.4) and T1 (P3.5) must be configured in an output mode ...
Page 34
... T0 is toggled at every TL0 overflow (see Figure 14-9 on page used to output a square wave of varying frequency. THx acts as an 8-bit counter. The following formula gives the output frequency for Timer 0 in PWM Mode 2. AT89LP213/214 34 Oscillator Frequency ------------------------------------------------------ - ...
Page 35
... TR1 ÷TPS OSC Control TR1 GATE INT1 Pin {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM Mode 2 and may be used as temporary storage registers. FFh THx Tx AT89LP213/214 RH1 (8 Bits) RL1 OCR1 (8 Bits) = TL1 TH1 (8 Bits) (8 Bits) TH1 ...
Page 36
... TH0. PWM Mode 3 is for applications requiring a single PWM channel and two timers, or two PWM channels and an extra timer or counter. With Timer 0 in PWM Mode 3, the AT89LP213 can appear to have three Timer/Counters. When Timer PWM Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3 ...
Page 37
... External Interrupts When the AT89LP213/214 is configured to use the internal RC Oscillator, XTAL1 and XTAL2 may be used as the INT0 and INT1 external interrupt sources. When the external clock source is used, XTAL2 is available as INT1. Neither interrupt is available in crystal oscillator mode. The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON ...
Page 38
... P1.x disabled 1 = interrupt for P1.x enabled . Table 16-4. – General-purpose Interrupt Flag Register GPIF GPIF = 9DH Not Bit Addressable GPIF7 GPIF6 Bit 7 6 GPIF interrupt on P1.x inactive 1 = interrupt on P1.x active. Must be cleared by software. AT89LP213/214 38 GPLS5 GPLS4 GPLS3 GPIEN5 GPIEN4 GPIEN3 GPIF5 GPIF4 ...
Page 39
... With SM2 = 1, no slave is interrupted by a data byte. An address byte, however, interrupts all slaves. Each slave can examine the received byte and see being addressed. The addressed slave clears its SM2 3538E–MICRO–11/10 AT89LP213/214 39 ...
Page 40
... Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the RI other modes, in any serial reception (except see SM2). Must be cleared by software. Notes: 1. SMOD0 is located at PCON. oscillator frequency. osc AT89LP213/214 40 See “Automatic Address Recognition” on page SM2 REN TB8 5 4 ...
Page 41
... Timer 1. Commonly Used Baud Rates Generated by Timer 1 (TPS = 0000B) f (MHz) OSC 11.059 9.6K 11.059 4.8K 11.059 2.4K 11.059 1.2K 11.059 137.5 11.986 110 6 110 12 AT89LP213/214 Oscillator Frequency = ------------------------------------------------------ - 2 SMOD1 2 × ------------------- - (Oscillator Frequency) 32 × (Timer 1 Overflow Rate) Oscillator Frequency 1 × × ------------------------------------------------------ - -------------------- - [ ( ) ] ...
Page 42
... As data bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded into the right-most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set. AT89LP213/214 42 shows a simplified functional diagram of the serial port in Mode 0 and associ- Figure 3538E– ...
Page 43
... Figure 17-1. Serial Port Mode 0 1/2 f osc WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) 3538E–MICRO–11/10 INTERNAL BUS “1“ INTERNAL BUS AT89LP213/214 43 ...
Page 44
... RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether or not the above conditions are met, the unit continues looking for a 1-to-0 transition in RXD. AT89LP213/214 and Either SM2 = 0, or the received stop bit = 1 ...
Page 45
... RX CLOCK SEND TI TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP213/214 TXD SHIFT D6 D7 STOP BIT STOP BIT 45 ...
Page 46
... SBUF. One bit time later, whether the above conditions were met or not, the unit continues look- ing for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. AT89LP213/214 46 show a functional diagram of the serial port in Modes 2 and 3. The ...
Page 47
... Figure 17-3. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3538E–MICRO–11/10 INTERNAL BUS INTERNAL BUS AT89LP213/214 47 ...
Page 48
... CLOCK WRITE TO SBUF SEND DATA SHIFT D0 D1 TXD START BIT TI STOP BIT GEN ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP213/214 48 INTERNAL BUS TB8 SBUF CL ZERO DETECTOR STOP BIT SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI ...
Page 49
... Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. 3538E–MICRO–11/10 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X AT89LP213/214 49 ...
Page 50
... UART drivers which do not make use of this feature. 18. Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89LP213/214 and peripheral devices or between multiple AT89LP213/214 devices. The SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • ...
Page 51
... Master MSB LSB MISO 8-Bit Shift Register MOSI SS GPIO GPIO SCK Clock Generator AT89LP213/214 Figure Slave MSB LSB MISO 8-Bit Shift Register MOSI DISSO SS SSIG SCK 18-1. The four 51 ...
Page 52
... Enable the master SPI prior to the slave device. 3. Slave echoes master on the next Tx if not loaded with new data. Table 18-2. SPDR – SPI Data Register SPDR Address = EAH Not Bit Addressable SPD7 SPD6 Bit 7 6 AT89LP213/214 52 DORD MSTR CPOL SPD5 SPD4 SPD3 ...
Page 53
... Enhanced SPI mode select bit. When ENH = 0, SPI is in normal mode, i.e. without write double buffering. ENH When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the SPDR register. 3538E–MICRO–11/10 LDEN – – AT89LP213/214 Reset Value = 000X X000B SSIG DISSO ENH ...
Page 54
... Figure 18-2. SPI Shift Register Diagram Serial In Transmit Byte Figure 18-3. SPI Block Diagram ÷4÷8÷32÷64 AT89LP213/214 54 7 Serial Master 8 2 MUX LATCH CLK 8 Parallel Master (Write Buffer LATCH CLK Oscillator MSB 8-bit Shift Register Read Data Buffer Divider Write Data Buffer ...
Page 55
... MASTER) MISO (FROM SLAVE) SS (TO SLAVE) Note: *Not defined but normally LSB of previously transmitted character. 3538E–MICRO–11/10 18-5. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL MSB MSB AT89LP213/214 LSB LSB 55 ...
Page 56
... Analog Comparator A single analog comparator is provided on the AT89LP213/214. The analog comparator has the following features: • Comparator Output Flag and Interrupt • Selectable Interrupt Condition – High- or Low-level – Rising- or Falling-edge – Output Toggle • Hardware Debouncing Modes Comparator operation is such that the output is a logic “1” when the positive input AIN0 (P1.0]) is greater than the negative input AIN1 (P1 ...
Page 57
... CIDL CF CEN 5 4 Interrupt Mode Negative (Low) level Positive edge (1) Toggle with debouncing (1) Positive edge with debouncing Negative edge Toggle (1) Negative edge with debouncing Positive (High) level CF Start Compare Start AT89LP213/214 Reset Value = XXX0 0000B CM3 CM1 Compare CM0 0 57 ...
Page 58
... WDTRST register and then 1EH to the WDTRST register. An incorrect feed or enable sequence will cause an immediate watchdog reset. The program sequence to feed or enable the watchdog timer is as follows: AT89LP213/214 58 14) The WDT is disabled by Reset and during Power-down mode. When the WDT for the available WDT period selections ...
Page 59
... Software Reset A Software Reset of the AT89LP213/214 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set ...
Page 60
... The AT89LP213/214 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP213/214 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP213/214 may take clock cycles to complete. The execution times of most instructions may be computed using Table 21-1 ...
Page 61
... SWAP A 3538E–MICRO–11/10 Instruction Execution Times and Exceptions (Continued) 1 Bytes AT89LP213/214 Clock Cycles 8051 AT89LP Hex Code 58- 56- ...
Page 62
... MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri AT89LP213/214 62 Instruction Execution Times and Exceptions (Continued) Bytes ...
Page 63
... CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP BREAK Note: 3538E–MICRO–11/10 Instruction Execution Times and Exceptions (Continued) Bytes Bytes (1) (1) 1. This escaped instruction is an extension to the instruction set. AT89LP213/214 Clock Cycles 8051 AT89LP ...
Page 64
... On-chip Debug System The AT89LP213/214 On-chip Debug (OCD) System uses a two-wire serial interface to control program flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete program flow control • Read-modify-write access to all internal SFRs and data memories • ...
Page 65
... XTAL1/P3.2. The INT0, INT1 and CLKOUT functions cannot be emulated in this mode. • The AT89LP213/214 does not support In-Application Programming and therefore the device must be reset before changing the program code during debugging. This includes the insertion/deletion of software breakpoints. ...
Page 66
... The ISP interface uses the SPI clock mode 0 (CPOL = 0,CPHA = 0) exclusively with a maximum frequency of 5 MHz. • The AT89LP213/214 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation recommended that the target reset can be controlled by the In-System programmer ...
Page 67
... Fuse is disabled, ISP may only be entered at POR. 23.2 Memory Organization The AT89LP213/214 offers 2K bytes of In-System Programmable (ISP) nonvolatile Flash code memory. In addition, the device contains a 64-byte User Signature Array and a 32-byte read- only Atmel Signature Array. The memory organization is shown in The memory is divided into pages of 32 bytes each. A single read or write command may only access a single page in the memory ...
Page 68
... Page oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP213/214 allocates 5 bits for byte address and 6 bits for page address. The page to be accessed is always fixed by the page address as transmitted ...
Page 69
... High Byte Input Address Low Byte Input/Output Address +1 Data Preamble 2 Opcode Address High X X AT89LP213/214 Address Low Data Data Out ...
Page 70
... Table 23-4 on page 71 6. Atmel Signature Bytes: AT89LP213: Address AT89LP214: Address 7. Symbol Key: a: Page Address Bit b: Byte Address Bit x: Don’t Care Bit AT89LP213/214 70 Opcode Addr High 1010 1100 0101 0011 1000 1010 – 0110 0000 xxxx xxxx 0101 0001 xxxx xxxx 0101 0000 ...
Page 71
... Flash Security The AT89LP213/214 provides two Lock Bits for Flash Code Memory security. Lock bits can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in 4. Lock bits can only be erased (set to FFh) by Chip Erase. Lock bit mode 2 disables program- ming of all memory spaces, including the User Signature Array and User Configuration Fuses ...
Page 72
... User Configuration Fuses The AT89LP213/214 includes 19 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in by programming 00h to their locations. Programming FFh to fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command ...
Page 73
... Power-on Reset to complete. The value of t SUT PWRUP RST SS SCK HIGH Z HIGH Z and bring SS high. SSD and then tristate SS and SCK. SSZ and power off VCC. PWRDN V CC RST SSD SSZ SCK AT89LP213/214 POR SUT ZSS t PWRDN HIGH Z HIGH Z Sec- will SUT 73 ...
Page 74
... ISP Exit Sequence Execute this sequence to exit ISP mode and resume CPU execution mode. 1. Drive SCK low. 1. Wait at least t 2. Tristate MOSI. 3. Wait at least t 4. Tristate SCK. 5. Wait t Figure 23-8. In-System Programming (ISP) Exit Sequence Note: AT89LP213/214 RLZ STL RLZ ...
Page 75
... MOSI 3538E–MICRO–11/10 Figure 23-9. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, SCK MOSI 7 6 MISO 7 6 Data Sampled SCK SSE t t SHSL t SOE AT89LP213/214 Figure 23-10 SLSH t t SOV SOH ...
Page 76
... SSE t SSD t ZSS t SSZ ERS Note: AT89LP213/214 76 Figure 23-5, Figure Table 23-6. Programming Interface Timing Parameters Parameter System Clock Cycle Time Power High Time Power-on Reset Time SS Tristate to Power Off RST Low to I/O Tristate RST Low Settling Time RST High to SS Tristate ...
Page 77
... OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89LP213/214 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...
Page 78
... A square wave generator with rail-to-rail output is used as an external clock source for consumption versus frequency measurements. 24.3.1 Supply Current (Internal Oscillator) Figure 24-1. Active Supply Current vs. V Figure 24-2. Idle Supply Current vs. VCC (8 MHz Internal Oscillator) AT89LP213/214 78 (8 MHz Internal Oscillator) CC Active Supply Current vs. VCC 8 MHz Internal Oscillator ...
Page 79
... Figure 24-4. Idle Supply Current vs. Frequency 3538E–MICRO–11/10 Active Supply Current vs. Frequency External Clock Source Frequency (MHz) Idle Supply Current vs. Frequency External Clock Source Frequency (MHz) AT89LP213/214 5.5V 5.0V 4.5V 3.6V 3.0V 2.4V 5.5V 5.0V 4.5V 3.3V 2.7V 2.4V 79 ...
Page 80
... Note: The data in this table was characterized on factory calibrated devices not tested during manufacturing and is provided for reference only. Devices may need to be recalibrated to target different operating conditions than the single-point factory calibration. AT89LP213/214 80 Internal Oscillator Frequency vs. VCC 8.4 8.3 8 ...
Page 81
... Figure 24-6. Quasi-Bidirectional Output I-V Characteristic at 5V Figure 24-7. Quasi-Bidirectional Output I-V Characteristic at 3V 3538E–MICRO–11/10 I/O DC Source Current vs. Output Voltage (VCC = 5V 2.0 2.5 3.0 3.5 0 -20 -40 -60 -80 -100 I/O DC Source Current vs. Output Voltage (VCC = 3V 0.0 0.5 1.0 1.5 -10 -20 -30 -40 -50 -60 -70 -80 AT89LP213/214 (V) 4.0 4.5 5.0 (V) 2.0 2.5 3.0 85C -40C 25C 85C -40C 25C 81 ...
Page 82
... Push-Pull Output Figure 24-8. Push-Pull Output I-V Characteristic at 5V Figure 24-9. Push-Pull Output I-V Characteristic at 3V Note: AT89LP213/214 82 I/O DC Source Current vs. Output Voltage (VCC = 5V) V OH1 -10 -12 I/O DC Source Current vs. Output Voltage (VCC = 3V) V OH1 0.0 0.5 1 -10 -12 Under DC operating conditions the Push-Pull Outputs exhibit reduced V atures due to the 5V tolerant port structure ...
Page 83
... Oscillator Amplitude vs. Frequency Quartz Crystal with R1 = 4MΩ Frequency (MHz) Oscillator Amplitude vs. Frequency Ceramic Resonator with R1 = 4MΩ Frequency (MHz) AT89LP213/214 C2=10pF C2=5pF C2=0pF C2=10pF C2=5pF C2=0pF 83 ...
Page 84
... External Clock Low Time CLCX t External Clock Rise Time CLCH t External Clock Fall Time CHCL Table 24-3. Clock Characteristics Symbol Parameter f Crystal Oscillator Frequency XTAL f Internal Oscillator Frequency IRC AT89LP213/214 84 Condition T = 25° 5. 2.4V to 5.5V CC Min Max Units 0 20 MHz 50 ns ...
Page 85
... Serial Output Hold Time SOH t Serial Output Valid Time SOV t Output Enable Time SOE t Output Disable Time SOX t Slave Enable Lead Time SSE t Slave Disable Lag Time SSD 3538E–MICRO–11/10 AT89LP213/214 Min Max 41.6 4t CLCL SCK SCK ...
Page 86
... SCK (CPOL = 1) MISO MOSI Figure 24-14. SPI Slave Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL= 1) MISO MOSI Figure 24-15. SPI Master Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI AT89LP213/214 SCK t t SHSL SLSH t t SLSH SHSL t t SOH SOV t t ...
Page 87
... XHDV Figure 24-17. Shift Register Mode Timing Waveform CLOCK WRITE TO SBUF OUTPUT DATA CLEAR RI INPUT DATA VALID 3538E–MICRO–11/10 = 2.4V to 5.5V and Load Capacitance = 80 pF VALID VALID VALID AT89LP213/214 Variable Oscillator Min Max 2t -15 CLCL t -15 CLCL t -15 CLCL ...
Page 88
... Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded V AT89LP213/214 88 (1) - 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at CC max. for a logic “ ...
Page 89
... XTAL1 RST (NC) XTAL2 CLOCK SIGNAL XTAL1 V SS Tests in Active and Idle Modes CHCL CHCX RST CC XTAL2 (NC) XTAL1 VSS AT89LP213/214 CLCH CHCL t CHCX t CLCH t CLCL = ...
Page 90
... AT89LP213-20PU AT89LP213-20XU 20 2.4V to 5.5V AT89LP214-20PU AT89LP214-20XU 14P3 14-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 14X 14-lead, 0.173” Wide, Plastic Thin Shrink Small Outline Package (TSSOP) AT89LP213/214 90 Package 14P3 14X 14P3 14X Package Type Operation Range Industrial (-40° 85° C) ...
Page 91
... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 3538E–MICRO–11/10 D PIN TITLE 14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) AT89LP213/214 E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM SYMBOL A – – A1 0.381 – D 18.669 – ...
Page 92
... TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AB-1. 0.65 (.0256) BSC 2325 Orchard Parkway San Jose, CA 95131 R AT89LP213/214 92 PIN 1 4.50 (0.177) 4.30 (0.169) 5.10 (0.201) 1.20 (0.047) MAX 4.90 (0.193) 0.15 (0.006) 0.30 (0.012) 0.05 (0.002) 0.19 (0.007) 0.20 (0.008) 0.09 (0.004) 0º~ 8º 0.75 (0.030) 0.45 (0.018) TITLE 14X (Formerly "14T"), 14-lead (4.4 mm Body) Thin Shrink ...
Page 93
... Updated Clock Parameters on page 84 • Removed standard packaging offering • Replaced C1 with R1 in oscillator diagram • Added oscillator input characteristics • Noted output levels as TTL. See AT89LP213/214 Figure 9-1 on page 12 Figure 9-2 on page 13 Figure 18-1 on page 51 page 72 page 72 page 78 page 80 page 81 Figure 9-1 on page 12. ...
Page 94
... AT89LP213/214 94 3538E–MICRO–11/10 ...
Page 95
... Block Diagram .......................................................................................... 5 5 Comparison to Standard 8051 ................................................................ 6 6 Memory Organization .............................................................................. 7 7 Special Function Registers ..................................................................... 9 8 Enhanced CPU ....................................................................................... 10 9 System Clock ......................................................................................... 12 10 Reset ....................................................................................................... 14 3538E–MICRO–11/10 2.1 AT89LP213: 14-lead TSSOP/PDIP ...................................................................2 2.2 AT89LP214: 14-lead TSSOP/PDIP ...................................................................2 5.1 System Clock .....................................................................................................6 5.2 Instruction Execution with Single-cycle Fetch ...................................................6 5.3 Interrupt Handling ..............................................................................................6 5.4 Timer/Counters ..................................................................................................6 5.5 Serial Port ..........................................................................................................6 5.6 Watchdog Timer ...
Page 96
... Table of Contents (Continued) 11 Power Saving Modes ............................................................................. 17 12 Interrupts ................................................................................................ 19 13 I/O Ports .................................................................................................. 23 14 Enhanced Timer/Counters .................................................................... 28 15 External Interrupts ................................................................................. 37 16 General-purpose Interrupts .................................................................. 37 17 Serial Interface ....................................................................................... 39 18 Serial Peripheral Interface ..................................................................... 50 19 Analog Comparator ............................................................................... 56 AT89LP213/214 ii 10.5 Software Reset ................................................................................................17 11.1 Idle Mode .........................................................................................................17 11.2 Power-down Mode ...........................................................................................17 12.1 Interrupt Response Time .................................................................................21 13.1 Port Configuration ............................................................................................24 13 ...
Page 97
... User Configuration Fuses ................................................................................72 23.8 Programming Interface Timing ........................................................................73 24.1 Absolute Maximum Ratings* ...........................................................................77 24.2 DC Characteristics ...........................................................................................77 24.3 Typical Characteristics ....................................................................................78 24.4 Clock Characteristics .......................................................................................84 24.5 Serial Peripheral Interface Timing ..................................................................85 24.6 Serial Port Timing: Shift Register Mode Test Conditions ................................87 24.7 Test Conditions ................................................................................................88 25.1 Green Package Option (Pb/Halide-free) ..........................................................90 26.1 14P3 – PDIP ....................................................................................................91 26.2 14X – TSSOP ..................................................................................................92 AT89LP213/214 iii ...
Page 98
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...