AT89LP4052 Atmel Corporation, AT89LP4052 Datasheet - Page 25

• Manufacturer Part Number: AT89LP4052
• Manufacturer: Atmel Corporation

Specifications of AT89LP4052

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 15
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI
• Watchdog: Yes

16.2
3547J–MICRO–10/09
Mode 1
a control bit in the Special Function Register TCON. GATE is in TMOD. The 13-bit register con-
sists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate
and should be ignored. Setting the run flag (TR1) does not clear the registers. See
Figure 16-1. Timer/Counter 1 Mode 0: Variable Width Counter
Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and INT0 replace
the corresponding Timer 1 signals in
Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
In Mode 1 the Timers are configured for 16-bit auto-reload. The Timer register is run with all 16
bits. The 16-bit reload value is stored in the high and low reload registers (RH1/RL1). The clock
is applied to the combined high and low timer registers (TH1/TL1). As clock pulses are received,
the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to-0000H
transition, upon which the timer register is reloaded with the value from RH1/RL1 and the over-
flow flag bit in TCON is set. See
the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for
Timer/Counter 0.
Figure 16-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload
INT1 Pin
INT1 Pin
T1 Pin
GATE
OSC
GATE
T1 Pin
OSC
TR1
TR1
C/T = 0
C/T = 1
C/T = 0
C/T =1
Figure
Control
Control
Figure
16-2. The reload registers default to 0000H, which gives
16-1. There are two different GATE bits, one for
(8 Bits)
TL1
(8 Bits)
(8 Bits)
RL1
TL1
AT89LP2052/LP4052
(8 Bits)
(8 Bits)
(8 Bits)
RH1
TH1
TH1
PSC1
Reload
TF1
TF1
Figure
Interrupt
Interrupt
16-1.
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