AT89LP4052 Atmel Corporation, AT89LP4052 Datasheet - Page 76

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AT89LP4052

Manufacturer Part Number
AT89LP4052
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89LP4052

Flash (kbytes)
4 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
15
Spi
1
Uart
1
Sram (kbytes)
0.25
Operating Voltage (vcc)
2.4 to 5.5
Timers
2
Isp
SPI
Watchdog
Yes

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23.5.4
23.5.5
76
AT89LP2052/LP4052
ISP Exit Sequence
ISP Byte Sequence
Execute this sequence to exit ISP and resume execution.
Figure 23-25. In-System Programming (ISP) Exit Sequence
Note:
The ISP byte sequence is shown in
Figure 23-26. ISP Byte Sequence
1. Bring SS (P1.4) to “H”.
2. Tri-state MOSI (P1.5).
3. Tri-state SCK (P1.7).
4. Bring RST to “L”.
5. Tri-state SS.
• Data shifts in/out MSB first.
• MISO changes at falling edge of SCK.
• MOSI is sampled at rising edge of SCK.
The waveforms on this page are not to scale.
MOSI
MISO
SCK
XTAL1
MISO
MOSI
RST
SCK
V
SS
CC
7
7
6
6
Data Sampled
Figure
5
5
23-26.
4
4
HIGH Z
HIGH Z
3
3
2
2
1
1
3547J–MICRO–10/09
0
0

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