AT89LP428 Atmel Corporation, AT89LP428 Datasheet
AT89LP428
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AT89LP428 Summary of contents
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... Push-pull CMOS Output • Open-drain • Operating Conditions – 2.4V to 5.5V V Voltage Range CC – -40°C to 85°C Temperature Range – MHz @ 2.4–5.5V – MHz @ 4.0–5.5V ® 51 Products 8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash AT89LP428 AT89LP828 3654A–MICRO–8/09 ...
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... CCD/P2 P2.0/CCA CCC/P2 P2.1/CCB 1.2 32A – 32-lead TQFP (Top View) XTAL2/P4.1 1 XTAL1/P4.0 2 P4.5 3 GND 4 P4.4 5 INT0/P3.2 6 INT1/P3.3 7 T0/P3.4 8 AT89LP428/828 2 1.3 32J – 32-lead PLCC XTAL2/P4.1 XTAL1/P4.0 P4.5 GND P4.4 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 1.4 32M1-A – 32-pad MLF (Top View) XTAL2/P4.1 24 P1.5/MOSI XTAL1/P4.0 23 P1.4/SS P4.5 22 P1.3 GND 21 P4 ...
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... Pin Description Table 1-1. AT89LP428/828 Pin Description Pin Number TQFP /MLF PLCC PDIP Symbol P4 P4 N/A P4 GND 5 9 N P1.0 3654A–MICRO–8/09 Type Description I/O P4 ...
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... Table 1-1. AT89LP428/828 Pin Description (Continued) Pin Number TQFP /MLF PLCC PDIP Symbol P1 P1 N/A P4 VCC 21 25 N P3.1 AT89LP428/828 4 Type Description I/O P1.1: User-configurable I/O Port 1 bit 1. ...
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... CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to exe- cute in 12 clock cycles. In the AT89LP428/828 CPU, instructions need only clock cycles providing times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock ...
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... Block Diagram Figure 2-1. AT89LP428/828 Block Diagram 4K/8K Bytes Flash Code General-purpose Interrupt Port 1 Configurable I/O Port 2 Configurable I/O Port 3 Configurable I/O Port 4 Configurable I/O POR BOD Crystal or Configurable Resonator Oscillator Internal RC Oscillator AT89LP428/828 6 512/1K Bytes 256 Bytes Flash Data RAM 8051 Single Cycle CPU 512 Bytes ...
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... Comparison to Standard 8051 The AT89LP428/828 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051 ...
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... UART Modes the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain the same baud rate in the AT89LP428/828 while running at the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud rates ...
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... SIG In addition to the 4K/8K code space, the AT89LP428/828 also supports a 128-byte User Signature Array and a 64-byte Atmel Signature Array that are accessible by the CPU. The Atmel Signature Array is initialized with the Device ID in the factory. The second page of the User Sig- nature Array (00C0H - 00FFH) is initialized with analog configuration data including the Internal RC Oscillator calibration byte ...
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... Internal Data Memory The AT89LP428/828 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. Access to the internal data memory does not require any configuration. The internal data memory has three address spaces: DATA, IDATA and SFR ...
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... External Data Memory AT89LP microcontrollers support a 16-bit external data memory address space. The external memory space is accessed with the MOVX instructions. The AT89LP428/828 does not support an external memory interface. However, some internal data memory resources are mapped into portions of the external address space as shown in require configuration before the CPU can access them ...
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... Avoiding unnecessary page erases greatly improves the endurance of the memory. The AT89LP428/828 includes 8/16 data pages of 64 bytes each. One or more bytes in a page may be written at one time. The AT89LP428/828 includes a temporary page buffer of 64 bytes, so the maximum number of bytes written at one time is 64 ...
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... Data Memory”. FDATA may also be programmed by an external device programmer (see gramming the Flash Memory” on page 3654A–MICRO–8/09 FDATA Byte Write DMEN MWEN LDPG IDLE t WC MOVX FDATA Page Write DMEN MWEN LDPG IDLE MOVX 115). AT89LP428/828 “Pro- 13 ...
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... In-Application Programming (IAP) The AT89LP428/828 supports In-Application Programming (IAP), allowing the program memory to be modified during execution. The IAP can be used to modify the user application on-the-fly or to use program memory for nonvolatile data storage. The same write protocol for FDATA also applies to IAP (see ing the program memory ...
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... User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 4-1. AT89LP428/828 SFR Map and Reset Values 8 9 0F8H ...
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... Enhanced CPU The AT89LP428/828 uses an enhanced 8051 CPU that runs times the speed of stan- dard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...
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... EX: • In some cases, both data pointers must be used simultaneously. To prevent frequent toggling of DPS, the AT89LP428/828 supports a prefix notation for selecting the opposite data pointer per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer. ...
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... Data Pointer Update The Dual Data Pointers on the AT89LP428/828 include two additional features that control how the data pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in DPCF, con- figure the INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as shown in Table 5-2 ...
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... CODE memory. Data Pointer Select. DPS selects the active data pointer for instructions that reference DPTR. When DPS = 0, DPTR will target DPTR0 and /DPTR will target DPTR1. When DPS = 1, DPTR will target DPTR1 and /DPTR will target DPTR0. AT89LP428/828 DPS = 1 /DPTR DPTR ...
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... Again, violating the memory boundaries may cause erratic execution. 5.2.2 MOVX-related Instructions The AT89LP428/828 contains 512 bytes of internal Extra RAM and 512/1024 bytes of Flash data memory mapped into the XRAM address space. MOVX accesses to addresses above 03FFH/05FFH will return invalid data. ...
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... Note that the internal structure of the Crystal Oscillator Connections 0–10 pF for Crystals = 0–10 pF for Ceramic Resonators R1 = 4–5 MΩ External Clock Drive Configuration NC, GPIO, or CLKOUT External Oscillator Signal AT89LP428/828 ~10 pF ~10 pF Figure 6-2. XTAL2 may be left unconnected, used as XTAL2 (P4.1) XTAL1 (P4.0) GND 21 ...
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... Internal RC Oscillator The AT89LP428/828 has an Internal RC oscillator (IRC) tuned to 8.0 MHz ±1.0% at 5.0V and 25 C. When enabled as the clock source, XTAL1 and XTAL2 may be used as P4.0 and P4.1, ° respectively. XTAL2 may also be configured to output a divided version of the system clock. The frequency of the oscillator may be adjusted within limits by changing the RC Calibration Byte stored at byte 64 of the User Signature Array ...
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... During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP428/828 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset. ...
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... The RST pin may be held low externally until these conditions are met. Figure 7-2. Time-out Internal Reset Internal Reset AT89LP428/828 24 Power-on Reset Sequence (BOD Disabled POR CC t ...
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... SUT Fuse 1 7.2 Brown-out Reset The AT89LP428/828 has an on-chip Brown-out Detector (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level V is nominally 2.2V. The purpose of the BOD is to ensure that if V speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution ...
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... WDTRST will generate an immediate reset and set both WDTOVF and SWRST to flag an error. 8. Power Saving Modes The AT89LP428/828 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. 8.1 Idle Mode Setting the IDL bit in PCON enters idle mode ...
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... After the rising edge on the pin the interrupt service routine will be executed. 3654A–MICRO–8/09 Interrupt Recovery from Power-down (PWDEX = 0) PWD XTAL1 INT1 Internal Clock 8-2. The interrupt pin should be held low long enough for the selected clock source to sta- AT89LP428/828 CC ) can also wake up the 7-0 Figure Table 7-1 on page t SUT has been 8-1. ...
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... CPU until after the timer has timed out. The time-out period is controlled by the Start-up Timer Fuses. (See clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will remain in reset until RST is brought high. Figure 8-3. . AT89LP428/828 28 Interrupt Recovery from Power-down (PWDEX = 1) PWD XTAL1 INT1 ...
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... Idle Mode Bit. Setting this bit activates Idle mode operation 9. Interrupts The AT89LP428/828 provides 10 interrupt sources: two external interrupts, three timer inter- rupts, a serial port interrupt, an analog comparator interrupt, a GPI, a compare/capture interrupt and an SPI interrupt. These interrupts and the system reset each have a separate program vec- tor at the start of the program memory space ...
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... System Reset External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port Interrupt Timer 2 Interrupt Analog Comparator Interrupt General-purpose Interrupt Compare/Capture Array Interrupt Serial Peripheral Interface Interrupt AT89LP428/828 30 Interrupt Vector Addresses Source RST or POR or BOD IE0 TF0 IE1 TF1 TF2 or EXF2 ...
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... Figure 9-2. 3654A–MICRO–8/09 Figure 9-1 and Figure 9-2. Minimum Interrupt Response Time Clock Cycles 1 INT0 IE0 Ack. Instruction Cur. Instr. Maximum Interrupt Response Time Clock Cycles 1 INT0 IE0 Instruction RETI AT89LP428/828 5 LCALL 1st ISR Instr. 14 Ack. 5 Cyc. Instr. LCALL 1st ISR Instr. 31 ...
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... Comparator Interrupt Priority Low PT2 Timer 2 Interrupt Priority Low PS Serial Port Interrupt Priority Low PT1 Timer 1 Interrupt Priority Low PX1 External Interrupt 1 Priority Low PT0 Timer 0 Interrupt Priority Low PX0 External Interrupt 0 Priority Low AT89LP428/828 32 ET2 ES ET1 PT2 PS PT1 ...
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... Serial Peripheral Interface Interrupt Enable ECC Compare/Capture Array Interrupt Enable EGP General-purpose Interrupt Enable 3654A–MICRO–8/09 PT2H PSH PT1H – – – AT89LP428/828 Reset Value = 0000 0000B PX1H PT0H PX0H Reset Value = xxxx x000B ESP ECC EGP ...
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... Interrupt Priority 3 Disable. Set IP3D disable all interrupts with priority level three. Clear enable all interrupts with priority level three when PSPH Serial Peripheral Interface Interrupt Priority High PCCH Compare/Capture Array Interrupt Priority High PGPH General-purpose Interrupt 0 Priority High AT89LP428/828 34 – – – – ...
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... I/O Ports The AT89LP428/828 can be configured for between 23 and 30 I/O pins. The exact number of I/O pins available depends on the package type and the clock and reset options as shown in Table 10-1. Table 10-1. Clock Source External Crystal or Resonator External Clock Internal RC Oscillator 10.1 Port Configuration All port pins on the AT89LP428/828 may be configured to one of four modes: quasi-bidirectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only ...
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... When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high. The quasi-bidirectional port configuration is shown in Figure 10-1. Quasi-bidirectional Output From Port Register AT89LP428/828 36 Port Configuration Registers Port Data Port Configuration 1 ...
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... Data PWD Input Data Figure 10-4. The input circuitry of P3.2, P3.3 and P3.6 is not disabled during Figure 10-3) and therefore these pins should not be left floating during Power- From Port Register AT89LP428/828 Figure 10-2. The output drivers are tristated. The Figure Port Pin Port Pin Input Data ...
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... Port 2 Analog Functions The AT89LP428/828 incorporates two analog comparators. In order to give the best analog per- formance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as described ...
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... SETB PX.Y 10.4 Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP428/828 share functionality with the various I/Os needed for the peripheral units. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwise the input/output will always be “ ...
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... Table 10-6. Port Pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P4.6 P4.7 AT89LP428/828 40 Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P1M0.0 P1M1.0 P1M0.1 P1M1.1 P1M0.2 P1M1.2 P1M0.3 P1M1.3 P1M0.4 P1M1.4 P1M0.5 P1M1.5 P1M0.6 P1M1.6 P1M0.7 P1M1.7 P2M0.0 P2M1.0 P2M0.1 P2M1.1 P2M0.2 P2M1.2 P2M0.3 P2M1.3 P2M0.4 P2M1.4 P2M0.5 P2M1.5 P2M0.6 P2M1 ...
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... Enhanced Timer 0 and Timer 1 with PWM The AT89LP428/828 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features: • Two 16-bit timer/counters with 16-bit reload registers • Two independent 8-bit precision PWM outputs with 8-bit prescalers • UART or SPI baud rate generation using Timer 1 • ...
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... RH1/RL1 and the overflow flag bit in TCON is set. See gives the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for Timer/Counter 0. AT89LP428/828 42 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count Mode 0: ...
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... Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of Mode 2: Time-out Period ÷TPS OSC C C Pin TR1 GATE INT0 Pin RH1/RL1 are not required by Timer 1 during Mode 2 and may be used as temporary storage registers. AT89LP428/828 RL1 RH1 (8 Bits) (8 Bits) Reload TL1 TH1 TF1 (8 Bits) (8 Bits 256 TH0 – ...
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... Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP428/828 can appear to have three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
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... Interrupt 0 Edge Flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT0 Interrupt 0 Type Control Bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. 3654A–MICRO–8/09 TF0 TR0 IE1 AT89LP428/828 Reset Value = 0000 0000B IT1 IE0 IT0 ...
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... AT89LP428/828 46 T1M1 T1M0 GATE0 Timer 1 Operation Variable 9 – 16-bit Timer mode. 8-bit Timer/Counter TH1 with TL1 8-bit prescaler. 16-bit Auto-reload mode. TH1 and TL1 are cascaded to form a 16-bit Timer/Counter that is reloaded with RH1 and RL1 each time it overflows. ...
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... TL0 for compatibility with the 13-bit Mode 0 in AT89C52. 11.5 Pulse Width Modulation On the AT89LP428/828, Timer 0 and Timer 1 may be independently configured as 8-bit asym- metrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM mode the generated waveform is output on the timer's input pin T1. Therefore, C/Tx must be set to “ ...
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... THx overflow, the duty cycle value in RHx is transferred to OCRx and the output pin is set high. When the count in THx matches OCRx, the output pin is cleared low. The following formulas give the output frequency and duty cycle for Timer 0 in PWM mode 1. Timer 1 in PWM mode 1 is identical to Timer 0. AT89LP428/828 48 Oscillator Frequency ------------------------------------------------------ - ...
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... Mode OUT ÷TPS OSC Control TR1 GATE INT1 Pin {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM mode 2 and may be used as temporary storage registers. AT89LP428/828 RH1 (8 Bits) RL1 OCR1 (8 Bits) = TL1 TH1 (8 Bits) (8 Bits) 1 × ...
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... TH0. PWM mode 3 is for applications requiring a single PWM channel and two timers, or two PWM channels and an extra timer or counter. With Timer 0 in PWM mode 3, the AT89LP428/828 can appear to have three Timer/Counters. When Timer PWM mode 3, Timer 1 can be turned on and off by switching it out of and into its own mode 3 ...
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... Figure 11-10. Timer/Counter 0 PWM Mode 3 3654A–MICRO–8/09 ÷TPS OSC Control TR0 GATE INT0 Pin ÷TPS OSC TR1 AT89LP428/828 RL0 (8 Bits) OCR0 = T0 TL0 (8 Bits) RH0 (8 Bits) OCR1 = T1 TH0 (8 Bits) 51 ...
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... Enhanced Timer 2 The AT89LP428/828 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate generation • Output-pin toggle on timer overflow • ...
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... RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. 3654A–MICRO–8/09 Table 12-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the RCLK TCLK EXEN2 AT89LP428/828 Table 12-3) and Reset Value = 0000 0000B TR2 C/T2 CP/RL2 ...
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... Timer 2 Output Enable. When T2OE = 1 and C/ the T2 pin will toggle after every Timer 2 overflow. DCEN Timer 2 Down Count Enable. When Timer 2 operates in Auto-reload mode and EXEN2 = 1, setting DCEN = 1 will cause Timer 2 to count up or down depending on the state of T2EX. AT89LP428/828 54 PHS1 PHS0 ...
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... Down Down Up-down Up-down AT89LP428/828 65536 × ( ------------------------------------------------------ - = Oscillator Frequency TL2 TH2 OVERFLOW TR2 CAPTURE RCAP2L RCAP2H EXF2 Table 12-5. Behavior → Up BOTTOM MAX reload to BOTTOM → MAX BOTTOM underflow to MAX → ...
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... The value of TOP stored in RCAP2H and RCAP2L is double-buffered such that a new TOP value takes affect only after an overflow. The behavior of Count Mode 0 versus Count Mode 1 is shown in Figure 12-2. Timer 2 Diagram: Auto-reload Mode (DCEN = 0) AT89LP428/828 56 shows Timer 2 automatically counting up when DCEN = 0 and T2CM Time-out Period = 01B ...
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... MAX and set the TF2 bit. This overflow 1-0 = 01B, the timer will overflow at TOP and set the TF2 bit. This 1-0 (Down Counting Reload Value) ÷TPS (Up Counting Reload Value) AT89LP428/828 TF2 Set = 00B, DCEN = 0 1-0 TF2 Set = 01B, DCEN = 0 1-0 Figure 12-4 ...
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... EXF2 bit to determine if TF2 was set at TOP or MIN. These count modes are pro- vided to support variable precision symmetrical PWM in the CCA. DCEN has no effect when using dual slope operation. The Timer 2 overflow rate for this mode is given in the following equation: Auto-Reload Mode: DCEN = 0, T2CM = 10B AT89LP428/828 58 Max Bottom T2CM Min ...
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... Note that the baud rates for transmit and receive can be different if Timer 2 is Modes 1 and 3 Baud Rates Modes 1, 3 T2CM = 00B = -------------------------------------------------------------------------------------------------------------------------------- - 16 Baud Rate Modes 1, 3 T2CM = 01B = ------------------------------------------------------------------------------------------------------------------ - 16 Baud Rate AT89LP428/828 T2CM = 10B 1-0 T2CM = 11B 1-0 Figure Timer 2 Overflow Rate = ----------------------------------------------------------- - 16 Oscillator Frequency × ...
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... Timer 2 is used as a baud-rate generator possible to use Timer baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. AT89LP428/828 60 ÷TPS C/ ...
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... Figure 12-8. Timer 2 in Clock-out Mode 13. Compare/Capture Array The AT89LP428/828 includes a four channel Compare/Capture Array (CCA) that performs a variety of timing operations including input event capture, output compare waveform generation and pulse width modulation (PWM). Timer 2 serves as the time base for the four 16-bit com- pare/capture modules. The CCA has the following features: • ...
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... T2CCH between T2CCL writes. Every write to T2CCL will use the last value of T2CCH for the upper data byte not possible to write to the data register of a channel config- ured for capture mode. The configuration bits for each channel are stored in the CCCx registers accessible through T2CCC. See AT89LP428/828 62 RCAP2L ÷TPS C/ ...
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... C – T2CCH, T2CCL and T2CCC access data and control for Channel C D – T2CCH, T2CCL and T2CCC access data and control for Channel D T2CCD.13 T2CCD.12 T2CCD. T2CCD.5 T2CCD.4 T2CCD AT89LP428/828 Reset Value = xxxx xx00B – T2CCA.1 T2CCA Reset Value = 0000 0000B T2CCD.10 T2CCD.9 T2CCD ...
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... All writes/reads to/from T2CCC will access channel X as currently selected by T2CCA.The control registers for the remain- ing unselected channels are not accessible. 2. Analog Comparator A events are determined by the CMA 3. Analog Comparator B events are determined by the CMB 4. Asymmetrical versus Symmetrical PWM is determined by the Timer 2 Count Mode. See page 68. AT89LP428/828 64 – CTCx CCMx 5 4 ...
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... CCFD CTCx “0” Timer 0 Overflow 4 Timer 1 Overflow 5 Comparator A 6 Comparator B 7 CxM 2-0 AT89LP428/828 Reset Value = XXXX 0000B CCFC CCFB CCFA bits in CCCx and may be either externally or 2-0 Figure 00H 00H TL2 TH2 CIENx CCxL CCxH CCFx CCCx ...
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... Timer 2 (TH2 and TL2). The compare event also sets the channel’s interrupt flag CCFx in T2CCF and may optionally clear Timer 2 to 0000H if the CTCx bit in CCCx is set. A diagram of a CCA channel in compare mode is shown in Figure 13-3. CCA Compare Mode Diagram AT89LP428/828 66 00H 00H ...
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... CTC mode. 3654A–MICRO–8/09 2-0 CP/RL2 = 0, T2CM {CCAH,CCAL} {CCBH,CCBL} CCA CCB AT89LP428/828 bits in CCCx determine what action is taken when a “Pulse Width Modulation Mode” on page 68 Figure 13-4 shows an example of outputting = 01B, DCEN = 0 1-0 Figure 13-5 shows an example wave- ...
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... PWM is intended for use with Timer 2 in Auto-reload mode (CP/RL2 = 0, DCEN = 0) using count modes The PWM can oper- ate in asymmetric (edge-aligned) or symmetric (center-aligned) mode depending on the T2CM selection. The CCA PWM has variable precision from bits. A trade-off between frequency AT89LP428/828 68 {CCAH,CCAL} CCA ...
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... CCxL CCxH CCCx T2CCL Shadow T2CCC T2CCH Figure 13-8. The timer counts up from BOTTOM to TOP and then restarts from BOT- Oscillator Frequency --------------------------------------------------------------- - f = OUT RCAP2H RCAP2L { Inverting: Duty Cycle Non-Inverting: Duty Cycle 100% = AT89LP428/828 CxM 2-0 CCFx CIENx 1 × -------------------- - 1 TPS CCxH CCxL , } × --------------------------------------------------------------- - = ...
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... TOP, the output will remain high or low for non- inverting and inverting modes, respectively. If the compare value is set to MIN (0000H), the out- put will remain low or high for non-inverting and inverting modes, respectively. AT89LP428/828 70 CP/RL2 = 0, T2CM ...
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... The = 11B, the Symmetrical PWM operates in phase correct mode. In this mode the 1-0 Figure 13-11 because the up and down count compare values may not be identical. CP/RL2 = 0, T2CM Inverted CCx AT89LP428/828 = 10B, DCEN = 0 1-0 = 10B, DCEN = 0 1-0 Duty Cycle Updated 71 ...
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... Multi-Phasic PWM The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS bits in T2MOD. The AT89LP428/828 provides 1 out out out of 4 and 2 out of 4 phase modes (see CCD are connected to a one-hot shift register that selectively enables and disables the outputs ...
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... CCD 3654A–MICRO–8/09 PHS = 010B PHS = 011B CCA CCB CCC CCD PHS = 000B PHS = 001B PHS = 010B PHS = 011B PHS = 100B AT89LP428/828 PHS = 100B CCA CCB CCC CCD CCA CCB CCC CCD 73 ...
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... CCC PHSD 14. External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP428/828 may be used as external interrupt sources. The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, inter- rupt request flag IEx in TCON is set ...
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... CLK GPMOD5 GPMOD4 GPMOD3 5 4 AT89LP428/828 GPIF Reset Value = 0000 0000B GPMOD2 GPMOD1 Interrupt GPMOD0 0 75 ...
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... P1.x disabled 1 = interrupt for P1.x enabled . Table 15-4. – General-purpose Interrupt Flag Register GPIF GPIF = 9DH Not Bit Addressable GPIF7 GPIF6 Bit 7 6 GPIF interrupt on P1.x inactive 1 = interrupt on P1.x active. Must be cleared by software. AT89LP428/828 76 GPLS5 GPLS4 GPLS3 GPIEN5 GPIEN4 GPIEN3 GPIF5 GPIF4 ...
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... Serial Interface (UART) The serial interface on the AT89LP428/828 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features: • Full-duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with Automatic Address Recognition • Baud Rate Generator Using Timer 1 or Timer 2 • ...
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... Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the RI other modes, in any serial reception (except see SM2). Must be cleared by software. Notes: 1. SMOD0 is located at PCON. oscillator frequency. The baud rate depends on SMOD1 (PCON.7). osc AT89LP428/828 78 SM2 REN TB8 ...
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... Mode 2 Baud Rate = 32 SMOD1 Mode 0 Baud Rate 2 × ------------------- - (Timer 1 Overflow Rate TB8 = 1 SMOD1 Modes × ------------------- - = (Timer 1 Overflow Rate) 32 Baud Rate SMOD1 Modes Oscillator Frequency × ------------------- - ------------------------------------------------------ - = [ 32 256 Baud Rate AT89LP428/828 Oscillator Frequency Oscillator Frequency 1 × -------------------- - ( ) ] – TH1 TPS + 1 79 ...
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... Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. In this case, the baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation:. Table 16-3 AT89LP428/828 80 SMOD1 Modes ...
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... OSC 62.5K 12 19.2K 11.059 9.6K 11.059 4.8K 11.059 2.4K 11.059 1.2K 11.059 137.5 11.986 110 6 110 12 Figure 16-1 on page 83 Mode 0 Baud Rates TB8 SMOD1 AT89LP428/828 Timer 2 C/T2 TCLK or RCLK shows a simplified functional diagram of Table 16-4 lists the baud rate options for Mode 0 ...
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... SMOD1 bits as listed in idle state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the output data is stable for both edges of the clock, or just one. Table 16-5. SM2 AT89LP428/828 82 Table 16-5 and shown in Mode 0 Clock and Data Modes SMOD1 Clock Idle 0 High ...
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... TIMER 1 OVERFLOW f osc 1 0 TB8 ÷2 ÷ SMOD1 WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) 3654A–MICRO–8/09 INTERNAL BUS “1“ INTERNAL BUS AT89LP428/828 SM2 83 ...
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... Write to SBUF Mode 0 transfers data LSB first whereas SPI or TWI are generally MSB first. Emulation of these interfaces may require bit reversal of the transferred data bytes. The following code example reverses the bits in the accumulator: EX: REVRS: RLC AT89LP428/828 84 TXD 0 1 RXD (TX) ...
Page 85
... On receive, the stop bit goes into RB8 in SCON. In the AT89LP428/828, the baud rate is determined either by the Timer 1 overflow rate, the TImer 2 overflow rate, or both. In this case one timer is for transmit and the other is for receive. ...
Page 86
... DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 TXD START BIT TI ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP428/828 86 INTERNAL BUS “1” SBUF CL ZERO DETECTOR SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI TI SERIAL PORT ÷ ...
Page 87
... SBUF. One bit time later, whether the above conditions were met or not, the unit continues look- ing for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. 3654A–MICRO–8/09 show a functional diagram of the serial port in Modes 2 and 3. The AT89LP428/828 87 ...
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... Figure 16-5. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 AT89LP428/828 88 INTERNAL BUS INTERNAL BUS 3654A–MICRO–8/09 ...
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... RX CLOCK SEND TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP428/828 TXD SHIFT D6 D7 TB8 STOP BIT RB8 STOP BIT 89 ...
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... A unique address for slave 1 would be 1100 0001 since a “1” in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. AT89LP428/828 90 SADDR = 1100 0000 ...
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... Enhanced Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT89LP428/828 and peripheral devices or between multiple AT89LP428/828 devices, including multiple masters and slaves on a single bus. The SPI includes the following features: • Full-duplex, 3-wire or 4-wire Synchronous Data Transfer • ...
Page 92
... Shift Register.The slave may ignore SS by setting its SSIG bit in SPSR. When SSIG = 1, the slave is always enabled and operates in 3-wire mode. However, the slave output on MISO may still be disabled by setting DISSO = 1. AT89LP428/828 92 Oscillator MSB ...
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... Master Operation An SPI master device initiates all data transfers on the SPI bus. The AT89LP428/828 is config- ured for master operation by setting MSTR = 1 in SPCR. Writing to the SPI data register (SPDR) while in master mode loads the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register ...
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... Slave Operation When the AT89LP428/828 is not configured for master operation, MSTR = 0, it will operate as an SPI slave. In slave mode, bytes are shifted in through MOSI and out through MISO by a mas- ter device controlling the serial clock on SCK. When a byte has been transferred, the SPIF flag is set to “ ...
Page 95
... Input (Tristate) (1) Output Input (External Pull-up) Output ( Input (Internal Pull-up) Internal Pull-up ( DISSO = 1) Output ( Input (Tristate) Tristated ( DISSO = 1) Input (Tristate) No output (Tristated) Output ( Input (External Pull-up) External Pull-up ( DISSO = 1) AT89LP428/828 Table 17-1. The user doesn’t 35. 95 ...
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... SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) Note: *Not defined but normally LSB of previously transmitted character. AT89LP428/828 96 17-4. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL, and MSB ...
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... SPI clock phase and polarity control. on SPI clock phase and polarity control. SCK (TSCK = T1OVF f /8 T1OVF f /32 T1OVF f /64 T1OVF AT89LP428/828 Reset Value = 00H (after cold reset) unchanged (after warm reset) SPD2 SPD1 SPD0 Reset Value = 0000 0000B CPHA SPR1 SPR0 2 1 ...
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... TX Buffer Interrupt Enable. When ENH = 1, TXE will generate an SPI interrupt if ESP = 1. When ENH = 0, TXE does not ENH generate an interrupt. 18. Dual Analog Comparators The AT89LP428/828 provides two analog comparators. The analog comparators have the fol- lowing features: • Internal 3-level Voltage Reference • Multiple Shared Analog Input Channels • ...
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... bits in ACSRx. The comparator interrupt flags CFx in ACSRx are set 2-0 and CBC bits in AREF control when the comparator interrupts sample the com- 1-0 1-0 AT89LP428/828 38. CMPB (P4.7) CMB2 CFB CMB1 CMB0 CMA2 CFA CMA1 EC CMA0 CMPA (P4.6) AREF+Δ AREF AREF-Δ ...
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... Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out periods later. See flows, i.e. CxC be accepted as an edge event. Figure 18-2. Negative Edge with Debouncing Example AT89LP428/828 100 or CSB bits in ACSRA and ACSRB. When changing the analog 1-0 1-0 EC ...
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... A CMPA - + A CMPA - + AIN3 CMPA AIN2 CSB = 11 RFB = 00 + AIN3 CMPA AREF CSB = 11 RFB = 10 AT89LP428/828 f. 2-channel window comparator with external reference CMPB - AIN2 B + AIN0 AIN3 + A - AIN1 CSA = CSB = 00/11 RFA = RFB = 00 g. 4-channel window comparator with internal reference - V AREF+Δ B AIN0 ...
Page 102
... Notes: 1. CONA must be cleared to 0 before changing CSA [1 - 0]. 2. Debouncing modes require the use of Timer 1 to generate the sampling delay. AT89LP428/828 102 CONA CFA CENA 5 4 (1) CMA0 Interrupt Mode 0 Negative (Low) level 1 Positive edge (2) 0 Toggle with debouncing ...
Page 103
... AIN1 (P2.5) AIN2 (P2.6) AIN3 (P2.7) CMB0 Interrupt Mode 0 Negative (Low) level 1 Positive edge (2) 0 Toggle with debouncing 1 Positive edge with debouncing 0 Negative edge 1 Toggle 0 Negative edge with debouncing 1 Positive (High) level AT89LP428/828 Reset Value = 1100 0000B CENB CMB2 CMB1 (2) (2) CMB0 0 103 ...
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... A-channel 0 0 AIN1 (P2. Internal Internal Internal V Notes: 1. CONB (ACSRB.5) must be cleared to 0 before changing RFB [1 - 0]. 2. CONA (ACSRA.5) must be cleared to 0 before changing RFA [1 - 0]. AT89LP428/828 104 RFB1 RFB0 CAC1 (1) (~1.2V) AREF-Δ (~1.3V) AREF (~1.4V) AREF+Δ (2) (~1.2V) AREF-Δ ...
Page 105
... PS1 The WDT time-out period is dependent on the system clock frequency. ------------------------------------------------------ - Time-out Period = Oscillator Frequency MOV WDTRST, #01Eh MOV WDTRST, #0E1h AT89LP428/828 (1) Period PS0 (Clock Cycles) 0 16K 1 32K 0 64K 1 128K 0 256K 1 512K 0 1024K 1 2048K ( ) PS ...
Page 106
... Software Reset A Software Reset of the AT89LP428/828 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set ...
Page 107
... The AT89LP428/828 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP428/828 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP428/828 may take clock cycles to com- plete. The execution times of most instructions may be computed using Table 20-1 ...
Page 108
... XRL A, #data XRL direct, A XRL direct, #data RL A RLC RRC A SWAP A Data Transfer MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data AT89LP428/828 108 Instruction Execution Times and Exceptions (Continued Bytes ...
Page 109
... Bytes AT89LP428/828 – – ...
Page 110
... JMP @A+DPTR JMP @A+PC CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel CJNE A, @R0, rel CJNE A, @R1, rel DJNZ Rn, rel DJNZ direct, rel NOP (1)(3) BREAK Notes: AT89LP428/828 110 Instruction Execution Times and Exceptions (Continued) Bytes ...
Page 111
... Table 10-3 on page 36 C6H Table 10-2 and C7H Table 10-2 and C0H Table 10-3 on page 36 BEH Table 10-2 and BFH Table 10-2 and 86H Table 3-3 on page 11 87H Table 8-1 on page 29 AT89LP428/828 Table 10-3 on page 36 Table 10-3 on page 36 Table 10-3 on page 36 Table 10-3 on page 36 Table 10-3 on page 36 Table 10-3 on page 36 Table 10-3 on page 36 Table 10-3 on page 36 111 ...
Page 112
... T2CCH T2CCL T2CON T2MOD TCON TCONB TH0 TH1 TH2 TL0 TL1 TL2 TMOD WDTCON WDTRST AT89LP428/828 112 Special Function Register Cross Reference (Continued) D0H CBH Section 12.1 on page 53 CAH Section 12.1 on page 53 94H Table 11-1 on page 41 95H Table 11-1 on page 41 92H Table 11-1 on page 41 93H Table 11-1 on page 41 A9H Section 16 ...
Page 113
... On-chip Debug System The AT89LP428/828 On-chip Debug (OCD) System uses a 2-wire serial interface to control pro- gram flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete program flow control • ...
Page 114
... OCD is disabled. 22.3 Limitations of On-chip Debug The AT89LP428/828 is a fully-featured microcontroller that multiplexes several functions on its limited I/O pins. Some device functionality must be sacrificed to provide resources for On-chip Debugging. The On-chip Debug System has the following limitations: • The Debug Clock pin (DCL) is physically located on that same pin as Port Pin P3.6 and the External Reset (RST) ...
Page 115
... SPI master, and the target system always operates as the SPI slave. To enter or remain in Programming mode the device’s reset line (RST) must be held active (low). With the addition of VCC and GND, an AT89LP428/828 microcontroller can be programmed with a mini- mum of seven connections as shown in Figure 23-1. In-System Programming Device Connections 3654A– ...
Page 116
... The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a maximum frequency of 5 MHz. • The AT89LP428/828 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation recommended that the target reset can be controlled by the In-System programmer ...
Page 117
... Page-oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP428/828 allocates 6 bits for byte address and 7 bits for page address. The page to be accessed is always fixed by the page address as transmitted. The byte address specifies the starting address for the first 3654A– ...
Page 118
... For a summary of available commands, see Figure 23-3. Command Sequence Flow Chart Figure 23-4. ISP Command Packet SS SCK MOSI Preamble 1 MISO X AT89LP428/828 118 Input Preamble 1 (AAH) Input Preamble 2 (55H) Input Opcode Input Address High Byte Input Address Low Byte ...
Page 119
... Fuse definitions. for Lock Bit definitions. 0001H 0002H 40H FFH 42H FFH AT89LP428/828 Addr Low Data 0 Data n – – – – xxxx xxxx Status Out 00bb bbbb DataIn 0 ... DataIn n aabb bbbb DataIn 0 ...
Page 120
... Flash Security The AT89LP428/828 provides two Lock Bits for Flash Code Memory security. Lock bits can be left unprogrammed (FFH) or programmed (00H) to obtain the protection levels listed in 5. Lock bits can only be erased (set to FFH) by Chip Erase. Lock bit mode 2 disables program- ming of all memory spaces, including the User Signature Array and User Configuration Fuses ...
Page 121
... User Configuration Fuses The AT89LP428/828 includes 11 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in by programming 00H to their locations. Programming FFH to a fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFH), the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command ...
Page 122
... IAP interface, equals the User Signature address plus 128 (0080H - 00FFH instead of 0000H - 007FH). The second page of the User Signature Array (0040H - 007FH) contains analog configuration parameters for the AT89LP428/828. Each byte represents a parameter as listed in 7 and is preset in the factory. The parameters are read at POR and the device is configured accordingly. The second page of the array is not affected by Chip Erase. Other bytes in this page may be used as additional signature space ...
Page 123
... MISO MOSI 3654A–MICRO–8/ PWRUP RST SS SCK HIGH Z HIGH Z and bring SS high. SSD and then tristate SS and SCK. SSZ and power off V PWRDN V CC RST SSD SSZ SCK AT89LP428/828 POR SUT ZSS . cc t PWRDN HIGH Z HIGH Z 123 ...
Page 124
... ISP Exit Sequence Execute this sequence to exit ISP mode and resume CPU execution mode. 1. Drive SCK low. 1. Wait at least t 2. Tristate MOSI. 3. Wait at least t 4. Tristate SCK. 5. Wait t Figure 23-8. In-System Programming (ISP) Exit Sequence Note: AT89LP428/828 124 + t . RLZ STL RLZ ...
Page 125
... Figure 23-9. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, CPHA = Figure SCK MOSI 7 6 MISO 7 6 Data Sampled SCK SSE t t SHSL t SOE AT89LP428/828 23-10 SLSH t t SOV SOH t ...
Page 126
... SSE t SSD t ZSS t SSZ AWR t ERS Note: AT89LP428/828 126 Figure 23-5, Figure Table 23-8. Programming Interface Timing Parameters Parameter System Clock Cycle Time Power High Time Power-on Reset Time SS Tristate to Power Off RST Low to I/O Tristate RST Low Settling Time RST High to SS Tristate ...
Page 127
... OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89LP428/828 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...
Page 128
... A square wave generator with rail-to-rail output is used as an external clock source for consumption versus frequency measurements. 24.3.1 Supply Current (Internal Oscillator) Figure 24-1. Active Supply Current vs. Vcc (8 MHz Internal Oscillator) Figure 24-2. Idle Supply Current vs. Vcc (8 MHz Internal Oscillator) AT89LP428/828 128 ...
Page 129
... Supply Current (External Clock) Figure 24-3. Active Supply Current vs. Frequency Figure 24-4. Idle Supply Current vs. Frequency 3654A–MICRO–8/ Frequency (MHz Frequency (MHz) AT89LP428/828 5.5V 5.0V 4.5V 3.6V 3.0V 2.4V 5.5V 5.0V 4.5V 3.6V 3.0V 2.4V 129 ...
Page 130
... Crystal Oscillator Figure 24-5. Quartz Crystal Input at 5V Figure 24-6. Ceramic Resonator Input at 5V AT89LP428/828 130 Oscillator Amplitude vs. Frequency Quartz Crystal with R1 = 4MΩ Frequency (MHz) Oscillator Amplitude vs. Frequency Ceramic Resonator with R1 = 4MΩ ...
Page 131
... Quasi-Bidirectional Input Figure 24-7. Quasi-bidirectional Input Transition Current at 5V Figure 24-8. Quasi-bidirectional Input Transition Current at 3V 3654A–MICRO–8/09 0.0 0.5 1.0 1.5 2.0 2.5 0 -50 -100 -150 -200 V IL 0.0 0.5 1.0 1.5 0 -20 -40 -60 -80 -100 V IL AT89LP428/828 3.0 3.5 4.0 4.5 5.0 (V) 2.0 2.5 3.0 (V) 85C -40C 25C 85C -40C 25C 131 ...
Page 132
... Reset Pull-up Resistor RST V Power-On Reset Threshold POR V Brown-Out Detector Threshold BOD V Brown-Out Detector Hysteresis BH t Power-On Reset Delay POR t Watchdog Reset Pulse Width WDTRST AT89LP428/828 132 = -40°C to 85°C and V = 2.4 to 5.5V, unless otherwise noted 2.4V to 5.5V CC Min Max ...
Page 133
... V = 2.4 to 5.5V, unless otherwise noted Min 50 4t CLCL SCK SCK 10 10 Min 50 4t CLCL 1 CLCL 1 CLCL AT89LP428/828 Max Units Max Units ...
Page 134
... SCK (CPOL = 1) MISO MOSI Figure 24-11. SPI Slave Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL= 1) MISO MOSI Figure 24-12. SPI Master Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI AT89LP428/828 134 SCK t t SHSL SLSH t t SLSH SHSL t t SOH SOV t t ...
Page 135
... V = 2.4 to 5.5V, unless otherwise noted Condition – mV 2.4V IN+ IN- CC 3.0 3.5 4.0 4.5 5.0 Vcc (V) AT89LP428/828 Min Max GND 1.2 1.3 70 170 200 3 Vref+ (85C) Vref+ (25C) Vref+ (-40C) Vref (85C) Vref (25C) Vref (-40C) Vref- (-40C) Vref- (25C) Vref- (85C) 5 ...
Page 136
... V IH (1) 24.9.2 Float Waveform Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded V AT89LP428/828 136 = 2.4V to 5.5V and Load Capacitance = 80 pF ...
Page 137
... GND RST (NC) XTAL2 CLOCK SIGNAL XTAL1 GND Tests in Active and Idle Modes CHCL CHCX RST CC (NC) XTAL2 XTAL1 GND AT89LP428/828 CLCH CHCL t CHCX t CLCH t CLCL = 137 ...
Page 138
... Ordering Code AT89LP428-20AU AT89LP428-20PU AT89LP428-20JU AT89LP428-20MU 20 2.4V to 5.5V AT89LP828-20AU AT89LP828-20PU AT89LP828-20JU AT89LP828-20MU AT89LP428-25AU AT89LP428-25PU AT89LP428-25JU AT89LP428-25MU 25 4.0V to 5.5V AT89LP828-25AU AT89LP828-25PU AT89LP828-25JU AT89LP828-25MU 32A 32-lead, Thin Plastic Quad Flat Package (TQFP) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32M1-A 32-pad ...
Page 139
... Orchard Parkway San Jose, CA 95131 R 3654A–MICRO–8/09 B PIN 1 IDENTIFIER TITLE 32A, 32-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) AT89LP428/828 A2 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM SYMBOL A – – A1 0.05 – ...
Page 140
... PDIP A SEATING PLANE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89LP428/828 140 D PIN PLACES 0º ~ 15º REF eB TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual ...
Page 141
... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3654A–MICRO–8/09 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) AT89LP428/828 0.318(0.0125) 0.191(0.0075 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 3.175 – ...
Page 142
... Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R AT89LP428/828 142 TITLE 32M1-A, 32-pad 1.0 mm Body, Lead Pitch 0.50 mm, 3 ...
Page 143
... Revision History Revision No. Revision A – August 2009 3654A–MICRO–8/09 History • Initial Release AT89LP428/828 143 ...
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... AT89LP428/828 144 3654A–MICRO–8/09 ...
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Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 5 3 Memory Organization .............................................................................. 8 4 Special Function Registers ................................................................... 15 5 Enhanced CPU ....................................................................................... 16 6 System Clock ......................................................................................... 20 7 Reset ....................................................................................................... 23 3654A–MICRO–8/09 1.1 28P3 ...
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Power Saving Modes ............................................................................. 26 8.1 Idle Mode .........................................................................................................26 8.2 Power-down Mode ...........................................................................................27 9 Interrupts ................................................................................................ 29 9.1 Interrupt Response Time .................................................................................31 9.2 Interrupt Registers ...........................................................................................32 10 I/O Ports .................................................................................................. 35 10.1 Port Configuration ............................................................................................35 10.2 Port 2 Analog ...
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Enhanced Serial Peripheral Interface .................................................. 91 18 Dual Analog Comparators ..................................................................... 98 19 Programmable Watchdog Timer ......................................................... 105 20 Instruction Set Summary .................................................................... 107 21 Register Index ...................................................................................... 111 22 On-chip Debug System ....................................................................... 113 23 Programming the Flash ...
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User Signature and Analog Configuration .....................................................122 23.9 Programming Interface Timing ......................................................................122 24 Electrical Characteristics .................................................................... 127 24.1 Absolute Maximum Ratings* .........................................................................127 24.2 DC Characteristics .........................................................................................127 24.3 Typical Characteristics ..................................................................................128 24.4 Clock Characteristics .....................................................................................132 24.5 Reset Characteristics ....................................................................................132 24.6 Serial ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Asia Atmel Europe ...