AT89LP6440 Atmel Corporation, AT89LP6440 Datasheet - Page 156

• Manufacturer Part Number: AT89LP6440
• Manufacturer: Atmel Corporation

Specifications of AT89LP6440

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

24.2
24.3
156
Software Breakpoints
Limitations of On-Chip Debug
AT89LP3240/6440
Figure 24-1. AT89LP3240/6440 On-Chip Debug Connections
The AT89LP3240/6440 microcontroller includes a BREAK instruction for implementing program
memory breakpoints in software. A software breakpoint can be inserted manually by placing the
BREAK instruction in the program code. Some emulator systems may allow for automatic inser-
tion/deletion of software breakpoints. The Flash memory must be re-programmed each time a
software breakpoint is changed. Frequent insertions/deletions of software breakpoints will
reduce the endurance of the nonvolatile memory. Devices used for debugging purposes should
not be shipped to end customers. The BREAK instruction is treated as a two-cycle NOP when
OCD is disabled.
The AT89LP3240/6440 is a fully-featured microcontroller that multiplexes several functions on
its limited I/O pins. Some device functionality must be sacrificed to provide resources for On-
Chip Debugging. The On-Chip Debug System has the following limitations:
• P4.2/RST cannot be connected directly to V
• All external reset sources must be removed.
• If P4.3 needs to be debugged in systems using the crystal oscillator, the external clock option
• The Debug Clock pin (DCL) is physically located on that same pin as Port Pin P4.2 and the
must be removed.
should be selected. The quartz crystal and any capacitors on XTAL1 or XTAL2 must be
removed and an external clock signal must be driven on XTAL1. Some emulator systems may
provide a user-configurable clock for this purpose.
External Reset (RST). Therefore, neither P4.2 nor an external reset source may be emulated
when OCD is enabled.
DDA
DCL
P4.2/RST
XTAL1
GND
CLK = Internal RC
A
DCL
VDD
CLK = Crystal Oscillator
P4.2/RST
XTAL2
XTAL1
GND
C
DD
DCL
CLK
and any external capacitors connected to RST
VDD
P4.3
CLK = External Clock
P4.2/RST
XTAL1
GND
DDA
B
XTAL2
VDD
3706C–MICRO–2/11
DDA