AT89S2051 Atmel Corporation, AT89S2051 Datasheet
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AT89S2051
Manufacturer Part Number
AT89S2051
Description
Manufacturer
Atmel Corporation
Specifications of AT89S2051
Flash (kbytes)
2 Kbytes
Max. Operating Frequency
24 MHz
Cpu
8051-12C
Max I/o Pins
15
Uart
1
Sram (kbytes)
0.25
Operating Voltage (vcc)
2.7 to 5.5
Timers
2
Isp
SPI
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Manufacturer
Quantity
Price
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ATMEL
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Errata
The following are known problems with Rev. A of the AT89S2051/S4051 device:
1. JBC to TF0, TF1, IE0, IE1
JBC may cause a loss of interrupt information if used with any interrupt flag (see item
#2 for SCON). Therefore JBC should not be used to poll for interrupt flags.
2. Read-Modify-Write to SCON (SETB, CLR, CPL, ANL, ORL, XRL, JBC)
Read-Modify-Write (RMW) instructions may cause a loss of UART interrupt informa-
tion if used with any bit in SCON, i.e. the RMW instructions need to be treated as a
direct move to SCON such as MOV SCON,#IMM. These instructions may be used
when it is not possible for the interrupt to occur at the same time as the instruction is
being executed, which means in the following circumstances::
3. Read-Modify-Write to ACSR (ANL, ORL, XRL)
Read-Modify-Write instructions may cause a loss of Comparator interrupt information
if used with any bit in ACSR, i.e. the RMW instructions need to be treated as a direct
move to ACSR such as MOV ACSR,#IMM. These instructions may be used when it is
not possible for the interrupt to occur at the same time as the instruction is being exe-
cuted, which means in the following circumstances:
4. Interrupt Recovery from Power-down Mode
When attempting interrupt recovery from power-down, the external interrupt pins INT0
(P3.2) and INT1 (P3.3) should not transition low until at least 10 µs after entry into
power-down. If the pins are low immediately before entering power-down, or go low
while attempting to enter power-down, the device can get stuck in a power-down-like
state requiring a power cycling sequence to wake up.
A. The UART is not currently operating, or
B. Within a short period of time after TI or RI is set during half-duplex communi-
C. Within a short period of time after both TI and RI are set during full-duplex
A. The Comparator is not active, or
B. Within a short period of time after CF is set, or
C. The flag is level-sensitive and the input condition will last through the next
D. Any time, if the application can afford to miss an edge event. The actual miss
POLL: JBC FLAG, NEXT
should be replaced by:
POLL: JNB FLAG, POLL
Problem Fix/Workaround:
cations, or
communications, and before the next byte is transmitted.
instruction, or
frequency will depend on the application code.
SJMP POLL
CLR FLAG
SJMP NEXT
AT89
Microcontrollers
AT89S2051
AT89S4051
Rev. A
Errata Sheet
3569A–MICRO–6/05
Related parts for AT89S2051
AT89S2051 Summary of contents
Page 1
... Errata The following are known problems with Rev the AT89S2051/S4051 device: 1. JBC to TF0, TF1, IE0, IE1 JBC may cause a loss of interrupt information if used with any interrupt flag (see item #2 for SCON). Therefore JBC should not be used to poll for interrupt flags. ...
Page 2
... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...