AT89S2051 Atmel Corporation, AT89S2051 Datasheet
AT89S2051
Specifications of AT89S2051
Available stocks
Related parts for AT89S2051
AT89S2051 Summary of contents
Page 1
... Hardware support for PWM with 8-bit resolu- tion and 8-bit prescaler is available by reconfiguring the two on-chip timer/counters. In addition, the AT89S2051/S4051 is designed with static logic for operation down to zero frequency and supports two software-selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning ...
Page 2
... The on-board Flash program memory is accessible through the ISP serial interface. Holding RST active forces the device into a serial programming interface and allows the program mem- ory to be written to or read from, unless one or more lock bits have been activated. 2. Pin Configuration 2.1 20-lead PDIP/SOIC 3. Block Diagram AT89S2051/S4051 2 RST/VPP 1 20 VCC (RXD) P3.0 ...
Page 3
... I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 also serves the functions of various special features of the AT89S2051/S4051 as listed below: Port Pin P3 ...
Page 4
... Figure 5-1. Note: Figure 5-2. AT89S2051/S4051 4 Connections C1 ± for Crystals = 5 pF ± for Ceramic Resonators External Clock Drive Configuration Figure 5-1 ...
Page 5
... In that case, the reset or inactive values of the new bits will always be 0. 3390E–MICRO–6/08 Figure 6-1 Clock Generation Block Diagram X2 Mode (XTAL1)/2 ÷ XTAL AT89S2051/S4051 shows the clock generation block diagram. State Machine: 6 Clock Cycles F CPU Control OSC 5 ...
Page 6
... Table 7-1. AT89S2051/S4051 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 0C8H 0C0H IP SADEN 0B8H X0X00000 00000000 P3 0B0H 11111111 IE SADDR 0A8H 00X00000 00000000 0A0H SCON SBUF 98H 00000000 XXXXXXXX P1 90H 11111111 TCON TMOD 88H ...
Page 7
... All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K/4K for the AT89S2051/S4051. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89S2051 (with 2K of memory), whereas LJMP 900H would not. 8.1 Branching Instructions LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR ...
Page 8
... Reset During reset, all I/O Registers are set to their initial values, the port pins are weakly pulled and the program starts execution from the Reset Vector, 0000H. The AT89S2051/S4051 CC has three sources of reset: power-on reset, brown-out reset, and external reset. 10.1 Power-On Reset A Power-On Reset (POR) is generated by an on-chip detection circuit ...
Page 9
... Brown-out Reset The AT89S2051/S4051 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD is nominally 2.0V. The purpose of the BOD is to ensure that if V speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution ...
Page 10
... Power Saving Modes The AT89S2051/S4051 supports two power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. 12.1 Idle Mode Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator ...
Page 11
... GF1, GF0 General-purpose Flags PD Power Down bit. Setting this bit activates power down operation. IDL Idle Mode bit. Setting this bit activates idle mode operation 3390E–MICRO–6/08 PWMEN POF GF1 AT89S2051/S4051 Reset Value = 000X 0000B GF0 PD IDL ...
Page 12
... Interrupts The AT89S2051/S4051 provides 6 interrupt sources: two external interrupts, two timer inter- rupts, a serial port interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register IE ...
Page 13
... External Interrupt 0 Priority High 3390E–MICRO–6/08 – ES ET1 – PS PT1 – PSH PT1H AT89S2051/S4051 Reset Value = 00X0 0000B EX1 ET0 EX0 Reset Value = X0X0 0000B PX1 PT0 PX0 Reset Value = X0X0 0000B PX1H PT0H PX0H 2 ...
Page 14
... Timer/Counters The AT89S2051/S4051 have two 16-bit Timer/Counters: Timer 0 and Timer 1. The Timer/Coun- ters are identical to those in the AT89C2051/C4051. For more detailed information on the Timer/Counter operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 16. Pulse Width Modulation Timer 0 and Timer 1 may be configured as an 8-bit pulse width modulator by setting the PWMEN bit in PCON ...
Page 15
... TL1 on overflow. Instead, TH1 is used strictly as a compare value (see Figure 16-3. Example of a PWM Output 17. UART The UART in the AT89S2051/S4051 operates the same way as the UART in the AT89C2051/C4051. For more detailed information on the UART operation, please click on the document link below: http://www ...
Page 16
... This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51-type UART drivers which do not make use of this feature. AT89S2051/S4051 16 SADDR = 1100 0000 ...
Page 17
... SM2 REN TB8 5 4 SM1 Mode Description 0 0 shift register 1 1 8-bit UART 0 2 9-bit UART 1 3 9-bit UART AT89S2051/S4051 Reset Value = 0000 0000B RB8 (2) Baud Rate f /12 osc variable f / /32 osc osc variable ...
Page 18
... Analog Comparator A single analog comparator is provided in the AT89S2051/S4051. The comparator operation is such that the output is a logical “1” when the positive input AIN0 (P1.0]) is greater than the neg- ative input AIN1 (P1.1). Otherwise the output is a zero. Setting the CEN bit in ACSR enables the comparator ...
Page 19
... Positive edge Toggle with debounce CM [2: Positive edge with debounce Negative edge Toggle Negative edge with debounce Positive (High) level 3390E–MICRO–6/08 – CF CEN AT89S2051/S4051 Reset Value = XXX0 0000B CM2 CM1 CM0 ...
Page 20
... Parallel Programming Specification Atmel’s AT89S2051/S4051 offers 2K/4K bytes of In-System Programmable Flash code memory. In addition, the device contains a 32-byte User Signature Row and a 32-byte read-only Atmel Signature Row. Table 21-1. Device # AT89S2051 AT89S4051 Figure 21-1. Flash Parallel Programming Device Connections Note: AT89S2051/S4051 20 Memory Organization ...
Page 21
... H 12V 0.1 µs 1.0 µs 12V L H 12V L Enable = 0/Disable = 1 Enable = 0/Disable = 1 Enable = 0/Disable = 1 Enable = 0/Disable = 1 Locked = 0/Unlocked = 1 Locked = 0/Unlocked = 1 00H = 1EH 01H = 23H 02H = FFH 00H = 1EH 01H = 43H 02H = FFH AT89S2051/S4051 Test Selects P3.3 P3.4 P3.5 P3 ...
Page 22
... Tri-state Port P1. 2. Bring RST/V 3. Bring XTAL and P3.2 to “L” and tri-state P3.7, P3.5, P3.4, and P3.3. 4. Bring RST to “L” and wait 10 µs. 5. Power off V Figure 23-1. Power-down Operation AT89S2051/S4051 22 has settled, wait 10 µs and bring RST to “H” 12V to enable the parallel programming modes. PP has settled, wait an additional 10 µ ...
Page 23
... Drive Port P1 with 8-bit X-address data. 3. Pulse XTAL1 high for at least 100 ns. The address is latched on the falling edge of XTAL1. Figure 25-1. Load X-Address Sequence 3390E–MICRO–6/08 This and the following waveforms are not to scale. P3.2 XTAL1 P3.3 - P3.7 P1.0 - P1.7 High Z RDY/BSY P3.2 XTAL1 P3.3 - P3.7 P1.0 - P1.7 High Z RDY/BSY AT89S2051/S4051 0001 1101 High Z XADDR 23 ...
Page 24
... For additional bytes (up to 32), pulse XTAL1 high for at least 100 ns to increment the Y-address and repeat steps 3 and 4 within 150 µs. 6. Wait 2 ms, monitor P3.1, or poll data. Note: Figure 26-1. Page Write 4K Code Programming Sequence P3.3 - P3.7 P1.0 - P1.7 RDY/BSY AT89S2051/S4051 possible to skip bytes by pulsing XTAL1 high multiple times before pulsing P3.2 low. P3.2 XTAL1 1101 XADDR DIN0 ...
Page 25
... For additional bytes (up to 32), pulse XTAL1 high for at least 100 ns to increment the Y-address and repeat step 3. The address will change on the falling edge of XTAL1. Figure 27-1. Read 4K Code Programming Sequence P3.3 - P3.7 P1.0 - P1.7 RDY/BSY 3390E–MICRO–6/08 P3.2 XTAL1 1101 XADDR DOUT0 AT89S2051/S4051 1100 DOUT N-1 DOUT1 25 ...
Page 26
... For additional bytes (up to 32), pulse XTAL1 high for at least 100 ns to increment the Y- address and repeat steps 3 and 4 within 150 µs. 6. Wait 2 ms, monitor P3.1, or poll data. Note: Figure 28-1. Page Write User Signature Row Sequence P3.3 - P3.7 P1.0 - P1.7 RDY/BSY AT89S2051/S4051 possible to skip bytes by pulsing XTAL1 high multiple times before pulsing P3.2 low. P3.2 XTAL1 1101 00H DIN0 ...
Page 27
... For additional bytes (up to 32), pulse XTAL1 high for at least 100 ns to increment the Y- address and repeat step 3. The address will change on the falling edge of XTAL1. Figure 29-1. Read User Signature Row Sequence P3.3 - P3.7 P1.0 - P1.7 RDY/BSY 3390E–MICRO–6/08 P3.2 XTAL1 1101 00H DOUT0 AT89S2051/S4051 1000 DOUT1 DOUT N-1 27 ...
Page 28
... Read 8-bit data on Port P1. 4. For additional bytes (up to 32), pulse XTAL1 high for at least 100 ns to increment the Y- address and repeat step 3. The address will change on the falling edge of XTAL1. Figure 30-1. Read Atmel Signature Row Sequence P3.3 - P3.7 P1.0 - P1.7 RDY/BSY AT89S2051/S4051 28 P3.2 XTAL1 1101 01H DOUT0 ...
Page 29
... Usage: 1. Apply “0011” TestCode to P3.7, P3.5, P3.4, P3.3. 2. Read fuse data from Port P1, bits [7:4] for fuses and bits [1:0] for lock bits. Figure 32-1. Read Lock Bits/User Fuses 3390E–MICRO–6/08 P3.2 XTAL1 P3.3 - P3.7 1111 P1.0 - P1.7 High Z DATA RDY/BSY P3.2 XTAL1 P3.3. - P3.7 0011 P1.0 - P1.7 High Z DOUT RDY/BSY AT89S2051/S4051 High Z High Z 29 ...
Page 30
... Figure 32-2. Flash Programming and Verification Waveforms in Parallel Mode AT89S2051/S4051 30 3390E–MICRO–6/08 ...
Page 31
... Data Setup to PROG Low Data Hold after PROG High XTAL1 Low to PROG Low PROG High to XTAL1 High Byte Load Period PROG High to BUSY Low Wire Cycle Time Read Byte Time XTAL1 Low to Data Verify Valid RST Low to Power Off AT89S2051/S4051 Min Max Units 11.5 12 µ ...
Page 32
... In-System Programming (ISP) Specification Atmel’s AT89S2051/S4051 offers 2K/4K bytes of In-System Programmable Flash code memory. In addition, the device contains a 32-byte User Signature Row and a 32-byte read-only Atmel Signature Row. Table 33-1. Device # AT89S2051 AT89S4051 Figure 33-1. ISP Programming Device Connections Note: AT89S2051/S4051 32 Memory Organization ...
Page 33
... Enable = 0/Disable = 1 Enable = 0/Disable = 1 Enable = 0/Disable = 1 Locked = 0/Unlocked = 1 Locked = 0/Unlocked = 1 00H = 1EH 01H = 23H 02H = FFH 00H = 1EH 01H = 43H 02H = FFH AT89S2051/S4051 Byte 3 Byte 4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0 0000 Data 0 ... Data 31 0 0000 Data 0 ... Data 31 xxxx xxxx ...
Page 34
... P1.7/SCK P1.6/MISO P1.5/MOSI 36. ISP Start Sequence Execute this sequence to enter ISP when the device is already operational. 1. Bring SCK (P1.7) to GND. 2. Tri-state MISO (P1.6). 3. Bring RST to “H”. Figure 36-1. ISP Start Sequence P1.7/SCK P1.6/MISO P1.5/MOSI AT89S2051/S4051 RST XTAL1 High RST XTAL1 High Z ...
Page 35
... All bytes are required, even if they are don’t care. Figure 39-1. ISP Command Sequence SCK SO 7 ??? SI 7 OPCODE 0 3390E–MICRO–6/ RST XTAL1 P1.7/SCK P1.6/MISO High Z P1.5/MOSI data is sampled ??? ADDRH 0 7 AT89S2051/S4051 High ??? 0 7 DATAOUT ADDRL 0 7 DATAIN ...
Page 36
... exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V P1.0 and P1.1 are comparator inputs and have no internal pullups. They should not be left floating. AT89S2051/S4051 36 *NOTICE: Condition (Except XTAL1, RST) (XTAL1, RST) (Ports mA 2.7V, T ...
Page 37
... External Clock Drive Waveforms 43. External Clock Drive Symbol Parameter 1/t Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL 3390E–MICRO–6/08 AT89S2051/S4051 V = 2.7V to 5.5V CC Min Max Units MHz ...
Page 38
... Input Data Valid to Clock Rising Edge XHDV 45. Shift Register Mode Timing Waveforms 46. AC Testing Input/Output Waveforms Note: (1) 47. Float Waveforms Note: AT89S2051/S4051 38 = 2.7V to 5.5V and Load Capacitance = 80 pF Inputs during testing are driven at V measurements are made at V min. for a logic 1 and ...
Page 39
... CLOCK SIGNAL XTAL1 RST CC P1, P3 (NC) XTAL2 CLOCK SIGNAL XTAL1 V SS Tests in Active and Idle Modes CHCL CHCX V RST CC P1, P3 (NC) XTAL2 XTAL1 VSS AT89S2051/S4051 CHCX t CLCH t CLCL ...
Page 40
... I (Active Mode) Measurements CC AT89S2051/S4051 40 I Active @ 25 CC 4.00 3.50 3.00 2.50 2.00 1. Frequency (MHz) I Active @ 90 CC 4.00 3.50 3.00 2.50 2.00 1. Frequency (MHz 3.0 V 4 3390E–MICRO–6/08 3.0V 4.0V 5.0V ...
Page 41
... I (Idle Mode) Measurements CC 54. I (Power Down Mode) Measurements CC 3390E–MICRO–6/08 I Idle vs. Frequency 25°C 3 2.5 2 1 Frequency (MHz Power-down CC 2.5 2 1 (V) CC AT89S2051/S4051 Vcc=3V Vcc=4V Vcc= deg C 25 deg C 90 deg ...
Page 42
... Ordering Code AT89S2051/S4051-24PU 24 2.7V to 5.5V AT89S2051/S4051-24SU 20P3 20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 20S2 20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC) AT89S2051/S4051 42 Package 20P3 20S2 Package Type Operation Range Industrial (-40° 85° C) 3390E–MICRO–6/08 ...
Page 43
... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 3390E–MICRO–6/08 D PIN TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) AT89S2051/S4051 E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM A – – A1 0.381 – D 24.892 – ...
Page 44
... SOIC AT89S2051/S4051 44 3390E–MICRO–6/08 ...
Page 45
... Revision History Revision No. Revision D – Feb. 2007 Revision E – June 2008 3390E–MICRO–6/08 AT89S2051/S4051 History • Removed Preliminary Status. • Added the qualifier “x1 and x2 Modes” to the Static Operation range. • Changed the value ranges for Capacitors C1 and page 4 ...
Page 46
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...