AT89S2051 Atmel Corporation, AT89S2051 Datasheet - Page 17
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AT89S2051
Manufacturer Part Number
AT89S2051
Description
Manufacturer
Atmel Corporation
Specifications of AT89S2051
Flash (kbytes)
2 Kbytes
Max. Operating Frequency
24 MHz
Cpu
8051-12C
Max I/o Pins
15
Uart
1
Sram (kbytes)
0.25
Operating Voltage (vcc)
2.7 to 5.5
Timers
2
Isp
SPI
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Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
ATMEL
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918
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Part Number:
AT89S2051-24PU
Manufacturer:
ATMEL
Quantity:
2 300
Part Number:
AT89S2051-24PU
Manufacturer:
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Company:
Part Number:
AT89S2051-24SU
Manufacturer:
MICROCHIP
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
Table 17-1.
Notes:
3390E–MICRO–6/08
SCON Address = 98H
Bit Addressable
Bit
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
(SMOD = 0/1)
1. SMOD is located at PCON.7.
2. f
SM0/FE
osc
Function
Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set
regardless of the state of SMOD.
Serial Port Mode Bit 0, (SMOD must = 0 to access bit SM0)
Serial Port Mode Bit 1
Enables the Automatic Address Recognition feature in modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received
9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In mode 1, if SM2 =
1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was
received. In mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the
stop bit in the other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop
bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
7
SCON – Serial Port Control Register
= frequency.
SM0
0
0
1
1
(1)
SM1
6
SM1
0
1
0
1
SM2
5
Mode
0
1
2
3
REN
4
shift register
Description
8-bit UART
9-bit UART
9-bit UART
TB8
3
f
osc
RB8
Baud Rate
2
/64 or f
variable
variable
f
osc
/12
AT89S2051/S4051
osc
Reset Value = 0000 0000B
(2)
/32
TI
1
RI
0
17