ATmega16HVA Atmel Corporation, ATmega16HVA Datasheet - Page 110
ATmega16HVA
Manufacturer Part Number
ATmega16HVA
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16HVA
Flash (kbytes)
16 Kbytes
Pin Count
28
Max. Operating Frequency
4 MHz
Cpu
8-bit AVR
# Of Touch Channels
3
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
256
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-20 to 85
I/o Supply Class
1.8 to 9.0
Operating Voltage (vcc)
1.8 to 9.0
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega16HVA-4TU
Manufacturer:
Atmel
Quantity:
20
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19.7.3
19.7.4
110
ATmega8HVA/16HVA
CADICH and CADICL - CC-ADC Instantaneous Current
CADAC3, CADADC2, CADAC1, CADAC0 - CC-ADC Accumulate Current
When a CC-ADC Instantaneous Current conversion is complete, the result is found in these two
registers. CADIC[15:0] represents the converted result in 2's complement format. CADIC[12:0]
are the 13-bit ADC result (including sign), while CADIC[15:13] are the sign extension bits.
When CADICL is read, the CC-ADC Instantaneous Current register is not updated until CADCH
is read. Reading the registers in the sequence CADICL, CADICH will ensure that consistent val-
ues are read. When a conversion is completed, both registers must be read before the next
conversion is completed, otherwise data will be lost.
The CADAC3, CADAC2, CADAC1 and CADAC0 Registers contain the Accumulate Current
measurements in 2's complement format. CADAC[17:0] are the 18-bit ADC result (including
sign), while CADAC[31:18] are the sign extension bits.
When CADAC0 is read, the CC-ADC Accumulate Current register is not updated until CADAC3
is read. Reading the registers in the sequence CADAC0, CADAC1, CADAC2, CADAC3 will
ensure that consistent values are read. When a conversion is completed, all four registers must
be read before the next conversion is completed, otherwise data will be lost.
Bit
(0xE9)
(0xE8)
Read/Write
Initial Value
Bit
(0xE3)
(0xE2)
(0xE1)
(0xE0)
Read/Write
Initial Value
15
R
R
31
23
15
7
0
0
R
R
R
7
0
0
0
14
30
22
14
R
R
6
0
0
R
R
R
6
0
0
0
13
29
21
13
R
R
5
0
0
R
R
R
5
0
0
0
12
28
20
12
CADAC[31:24]
CADAC[23:16]
R
R
4
0
0
R
R
R
4
CADAC[15:8]
0
0
0
CADIC[15:8]
CADAC[7:0]
CADIC[7:0]
11
27
19
11
R
R
3
0
0
R
R
R
3
0
0
0
10
26
18
10
R
R
2
0
0
R
R
R
2
0
0
0
25
17
R
R
R
R
R
9
1
0
0
9
1
0
0
0
24
16
R
R
R
R
R
8
0
0
0
8
0
0
0
0
8024A–AVR–04/08
CADAC3
CADAC2
CADAC1
CADAC0
CADICH
CADICL
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