ATmega16HVA Atmel Corporation, ATmega16HVA Datasheet - Page 18
ATmega16HVA
Manufacturer Part Number
ATmega16HVA
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16HVA
Flash (kbytes)
16 Kbytes
Pin Count
28
Max. Operating Frequency
4 MHz
Cpu
8-bit AVR
# Of Touch Channels
3
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
256
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-20 to 85
I/o Supply Class
1.8 to 9.0
Operating Voltage (vcc)
1.8 to 9.0
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega16HVA-4TU
Manufacturer:
Atmel
Quantity:
20
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8.4
8.4.1
8.5
18
EEPROM Data Memory
I/O Memory
ATmega8HVA/16HVA
EEPROM Read/Write Access
Figure 8-3.
The ATmega8HVA/16HVA contains 256 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of EEPROM programming, see
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
The I/O space definition of the ATmega8HVA/16HVA is shown in
175.
All ATmega8HVA/16HVA I/Os and peripherals are placed in the I/O space. All I/O locations may
be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the
32 general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
Address
clk
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
Compute Address
T1
Memory Access Instruction
Address valid
Table 8-1 on page
T2
page 151
Next Instruction
”Register Summary” on page
and
T3
20. A self-timing function,
page 156
8024A–AVR–04/08
respectively.
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