ATmega16M1 Atmel Corporation, ATmega16M1 Datasheet - Page 138

• Manufacturer Part Number: ATmega16M1
• Manufacturer: Atmel Corporation

Specifications of ATmega16M1

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5.3.2
138
ATmega16M1/32M1/64M1
Center Aligned Mode
In center aligned mode, the center of PSCOUTnA and PSCOUTnB signals are centered.
Figure 17-6. PSCOUTnA & PSCOUTnB Basic Waveforms in Center Aligned Mode
On-Time 0 = 2 × POCRnSAH/L × 1/Fclkpsc
On-Time 1 = 2 × (POCRnRBH/L - POCRnSBH/L + 1) × 1/Fclkpsc
Dead-Time = (POCRnSBH/L - POCRnSAH/L) × 1/Fclkpsc
PSC Cycle = 2 × (POCRnRBH/L + 1) × 1/Fclkpsc
Note:
Note that in center aligned mode, POCRnRAH/L is not required (as it is in one-ramp mode) to
control PSC Output waveform timing. This allows POCRnRAH/L to be freely used to adjust ADC
synchronization.
POCRnRB
POCRnSB
POCRnSA
PSCOUTnA
PSCOUTnB
Minimal value for PSC Cycle = 2 × 1/Fclkpsc
On-Time 1
See “Analog Synchronization” on page 145.
PSC Counter
Dead-Time
On-Time 0
PSC Cycle
0
Dead-Time
On-Time 1
8209D–AVR–11/10