ATmega16M1 Atmel Corporation, ATmega16M1 Datasheet - Page 149

• Manufacturer Part Number: ATmega16M1
• Manufacturer: Atmel Corporation

Specifications of ATmega16M1

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.16.6
17.16.7
8209D–AVR–11/10
POCRnRBH and POCRnRBL – PSC Output Compare RB Register
PCNF – PSC Configuration Register
Note: n = 0 to 2 according to module number
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously
compared with the PSC counter value. A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the associated pin.
The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by
all the other 16-bit registers.
• Bit 7:6 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 5 – PULOCK: PSC Update Lock
When this bit is set, the Output Compare Registers POCRnRA, POCRnSA, POCRnSB,
POCR_RB and the PSC Output Configuration Registers POC can be written without disturbing
the PSC cycles. The update of the PSC internal registers will be done if the PULOCK bit is
released to zero.
• Bit 4 – PMODE PSC Mode
Select the mode of PSC.
Table 17-10. PSC Mode Selection
• Bit 3 – POPB: PSC B Output Polarity
If this bit is cleared, the PSC outputs B are active Low.
If this bit is set, the PSC outputs B are active High.
• Bit 2 – POPA: PSC A Output Polarity
If this bit is cleared, the PSC outputs A are active Low.
If this bit is set, the PSC outputs A are active High.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PMODE
0
1
R/W
7
–
0
R
7
0
-
Description
One Ramp Mode (Edge Aligned)
Center Aligned Mode
R/W
6
–
0
R
6
0
-
PULOCK
R/W
R/W
5
–
0
5
0
PMODE
R/W
R/W
POCRnRB[7:0]
4
–
0
4
0
ATmega16M1/32M1/64M1
POPB
R/W
R/W
3
0
3
0
POPA
POCRnRB[11:8]
R/W
R/W
2
0
2
0
R/W
R
1
0
1
0
-
R/W
R
0
0
0
0
-
POCRnRBH
POCRnRBL
PCNF
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