ATmega324P Automotive Atmel Corporation, ATmega324P Automotive Datasheet - Page 67

• Manufacturer Part Number: ATmega324P Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega324P Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.2.2
11.2.3
7674F–AVR–09/09
EIMSK – External Interrupt Mask Register
EIFR –External Interrupt Flag Register
If low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate
an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can
occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in
the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should
be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the
interrupt is re-enabled.
Table 11-1.
Note:
• Bits 2:0 – INT2:0: External Interrupt Request 2 - 0 Enable
When an INT2:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the
corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External
Interrupt Control Register, EICRA, defines whether the external interrupt is activated on rising or
falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if
the pin is enabled as an output. This provides a way of generating a software interrupt.
• Bits 2:0 – INTF2:0: External Interrupt Flags 2 - 0
When an edge or logic change on the INT2:0 pin triggers an interrupt request, INTF2:0 becomes
set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT2:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT2:0 are configured as level interrupt. Note that when entering sleep
mode with the INT2:0 interrupts disabled, the input buffers on these pins will be disabled. This
may cause a logic change in internal signals which will set the INTF2:0 flags. See
Enable and Sleep Modes” on page 75
Bit
0x1D (0x3D)
Read/Write
Initial Value
Bit
0x1C (0x3C)
Read/Write
Initial Value
ISCn1
0
0
1
1
1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed
ISCn0
0
1
0
1
Interrupt Sense Control
R/W
R
7
–
0
7
–
0
Description
The low level of INTn generates an interrupt request.
Any edge of INTn generates asynchronously an interrupt request.
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
(1)
for more information.
R
R
4
–
0
4
–
0
ATmega164P/324P/644P
R
R
3
–
0
3
–
0
INTF2
INT2
R/W
R/W
2
0
2
0
INTF1
INT1
R/W
R/W
1
0
1
0
IINTF0
IINT0
R/W
R/W
0
0
0
0
“Digital Input
EIMSK
EIFR
67