ATmega328P Automotive Atmel Corporation, ATmega328P Automotive Datasheet - Page 86
ATmega328P Automotive
Manufacturer Part Number
ATmega328P Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATmega328P Automotive
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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14. 8-bit Timer/Counter0 with PWM
14.1
14.2
86
Features
Overview
ATmega328P [Preliminary]
•
•
•
•
•
•
•
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in
placement of I/O pins, refer to
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the
The PRTIM0 bit in
enable Timer/Counter0 module.
Figure 14-1. 8-bit Timer/Counter Block Diagram
Two Independent Output Compare Units
Double Buffered Output Compare Registers
Clear Timer on Compare Match (Auto Reload)
Glitch Free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
“Register Description” on page
Timer/Counter
“Minimizing Power Consumption” on page 40
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
“Pinout” on page
Direction
Count
Clear
97.
Control Logic
TOP
=
TCCRnB
Value
BOTTOM
Fixed
TOP
2. CPU accessible I/O Registers, including I/O
clk
=
Tn
0
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
( From Prescaler )
Waveform
Waveform
Detector
Figure
Edge
must be written to zero to
14-1. For the actual
7810A–AVR–11/09
OCnA
OCnB
Tn
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