ATmega32A Atmel Corporation, ATmega32A Datasheet - Page 151
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ATmega32A
Manufacturer Part Number
ATmega32A
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32A
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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19.3.2
19.3.3
19.3.4
8155C–AVR–02/11
Double Speed Operation (U2X)
External Clock
Synchronous Clock Operation
Table 19-1.
Note:
Some examples of UBRR values for some system clock frequencies are found in
(see
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect
for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and receiver. This process introduces
a two CPU clock period delay and therefore the maximum external XCK clock frequency is lim-
ited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
Operating Mode
Asynchronous Normal Mode
(U2X = 0)
Asynchronous Double Speed Mode (U2X
= 1)
Synchronous Master Mode
page
BAUD
f
UBRR
OSC
1. The baud rate is defined to be the transfer rate in bit per second (bps).
osc
172).
depends on the stability of the system clock source. It is therefore recommended to
Equations for Calculating Baud Rate Register Setting
Figure 19-2
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRH and UBRRL Registers, (0 - 4095)
for details.
BAUD
f
BAUD
BAUD
Equation for Calculating
XCK
<
Baud Rate
f
---------- -
=
OSC
=
=
4
-------------------------------------- -
16 UBRR
---------------------------------- -
8 UBRR
---------------------------------- -
2 UBRR
(
(
(
f
f
f
OSC
OSC
OSC
(1)
+
+
+
1
1
1
)
)
)
Equation for Calculating
UBRR
UBRR
UBRR
ATmega32A
UBRR Value
=
=
=
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
OSC
OSC
OSC
Table 19-9
–
–
–
151