ATmega48A Atmel Corporation, ATmega48A Datasheet
ATmega48A
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ATmega48A Summary of contents
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... Active Mode: 0.2mA – Power-down Mode: 0.1µA – Power-save Mode: 0.75µA (Including 32kHz RTC) ® ® AVR 8-Bit Microcontroller ( compatible) 8-bit Atmel Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash ATmega48A ATmega48PA ATmega88A ATmega88PA ATmega168A ATmega168PA ATmega328 ATmega328P Rev. 8271D–AVR–05/11 ...
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... PC1 (ADC1/PCINT9 PC0 (ADC0/PCINT8) 18 GND AREF 6 16 AVCC (PCINT6/XTAL1/TOSC1) PB6 15 PB5 (SCK/PCINT5) 7 (PCINT7/XTAL2/TOSC2) PB7 NOTE: Bottom pad should be soldered to ground. 32UFBGA - Pinout ATmega48A/48PA/88A/88PA/168A/168PA 1 2 PD2 PD1 PC6 PD3 PD4 PD0 GND GND VDD VDD PB6 PD6 PB0 PB7 PD5 PD7 ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”System Clock and Clock Options” on page Table 29-12 on page ”Alternate Functions of Port B” on page 27 ...
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... In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P , even if the ADC is not used. If the ADC is used, it should be connected ” ...
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... Overview The ATmega48A/PA/88A/PA/168A/PA/328 low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... Atmel ATmega48A/PA/88A/PA/168A/PA/328 powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega48A/PA/88A/PA/168A/PA/328/P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Sim- ulators, In-Circuit Emulators, and Evaluation kits ...
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... ATmega168PA ATmega328 ATmega328P ATmega48A/PA/88A/PA/168A/PA/328/P support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega 48A/48PA there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...
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... The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 1. ® QTouch ® ...
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... The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Block Diagram of the AVR Architecture Program Flash ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 ...
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... SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P shows the structure of the 32 general purpose working registers in the CPU. AVR CPU General Purpose Working Registers ...
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... Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P The X-, Y-, and Z-registers 15 XH ...
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... Instruction Execute 3rd Instruction Execute Figure 7-5 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 7-5. Register Operands Fetch ALU Operation Execute 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 SP15 SP14 SP13 SP7 SP6 ...
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... No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P for details. ”Interrupts” on page 59 ”Boot Loader Support – Read-While-Write Self-Programming” on page ” ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ...
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... AVR Memories 8.1 Overview This section describes the different memories in the ATmega48A/PA/88A/PA/168A/PA/328/P. The AVR architecture has two main memory spaces, the Data Memory and the Program Mem- ory space. In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
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... Figure 8-1. Figure 8-2. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Program Memory Map ATmega 48A/48PA Program Memory Application Flash Section Program Memory Map ATmega88A, ATmega88PA, ATmega168A, ATmega168PA, ATmega328 and ATmega328P Program Memory Application Flash Section Boot Flash Section 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF/0x3FFF ...
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... SRAM Data Memory Figure 8-3 organized. The ATmega48A/PA/88A/PA/168A/PA/328 complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... Figure 8-4. 8.4 EEPROM Data Memory The ATmega48A/PA/88A/PA/168A/PA/328/P contains 256/512/512/1Kbytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Reg- isters, the EEPROM Data Register, and the EEPROM Control Register. ” ...
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... The I/O space definition of the ATmega48A/PA/88A/PA/168A/PA/328/P is shown in Summary” on page All ATmega48A/PA/88A/PA/168A/PA/328/P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... EEDR contains the data read out from the EEPROM at the address given by EEAR. 8.6.3 EECR – The EEPROM Control Register Bit 0x1F (0x3F) Read/Write Initial Value • Bits 7:6 – Reserved These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 – ...
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... Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See Support – Read-While-Write Self-Programming” on page 280 programming. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P EEPROM Mode Bits Programming EEPM0 Time ...
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... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ...
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... Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ...
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... GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ...
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... USI module is carried out asynchronously when clk recognition in all sleep modes. Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P presents the principal clock systems in the AVR and their distribution. All of the clocks 40. The clock systems are detailed below. Clock Distribution ...
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... The delay (t Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. ...
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... Some initial guidelines for choosing capacitors for use with crystals are given in ues given by the manufacturer should be used. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Table 9-2. The frequency of the Watchdog Oscillator is voltage ”Typical Characteristics” on page Number of Watchdog Oscillator Cycles = 5 ...
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... Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Crystal Oscillator Connections C2 C1 30. Low Power Crystal Oscillator Operating Modes Recommended Range for (MHz) Capacitors C1 and C2 (pF) ...
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... The operating mode is selected by the fuses CKSEL3...1 as shown in Table 9-5. Frequency Range (MHz) Notes: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and Power-save 16K CK 16K CK 16K CK 1 ...
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... Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Crystal Oscillator Connections C2 C1 Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save ...
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... ATmega48A/PA/88A/PA/168A/PA/328/P oscillator is optimized for very low power consumption, and thus when selecting crystals, see 9 ...
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... Table 9-12. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save ( 32K CK 1. This option should only be used if frequency stability at start-up is not important for the application for more details ...
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... Figure 9-4. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-16. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 128kHz Internal Oscillator Operating Modes (1) Nominal Frequency 128kHz 1. Note that the 128kHz oscillator is a very low power clock source, and is not designed for high accuracy ...
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... System Clock Prescaler The ATmega48A/PA/88A/PA/168A/PA/328/P has a system clock prescaler, and the system clock can be divided by setting the ture can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low ...
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... Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 37 ...
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... These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchro- nous peripherals is reduced when a division factor is used. The division factors are given in Table 9-17 on page 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 ...
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... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 9-17. CLKPS3 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Clock Prescaler Select CLKPS2 CLKPS1 0 0 ...
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... See ”BOD Disable(1)” on page 41 10.1 Sleep Modes ATmega48A/PA/88A/PA/168A/PA/328/P, and their distribution. The figure is helpful in selecting an appropriate sleep mode. BOD disable ability. Note: Table 10-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. ...
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... Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode. Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Table 10-1 on page 40. The sleep mode power consumption will then be at the 46. ...
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... Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disap- pears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated ...
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... In the deeper sleep modes, this will contribute sig- nificantly to the total current consumption. Refer to on how to configure the Brown-out Detector. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”PRR – Power Reduction Register” on page ”Analog Comparator” on page 248 ”Analog-to-Digital Converter” on page 252 for details on how to configure the Analog ” ...
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... In the deeper sleep modes, this will contribute significantly to the total current consumption. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P for details on the start-up time. ”Watchdog Timer” on page 52 for details on how to configure the Watchdog Timer. ...
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... Read/Write Initial Value • Bits [7:4]: Reserved These bits are unused in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always be read as zero. • Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 10-2 ...
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... Bit 4 – Reserved This bit is reserved in ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero. • Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. 8271D– ...
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... Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 47 ...
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... Reset Sources The ATmega48A/PA/88A/PA/168A/PA/328/P has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
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... Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V Figure 11-2. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor SPIKE ...
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... Figure 11-4. External Reset During Operation 11.5 Brown-out Detection ATmega48A/PA/88A/PA/168A/PA/328/P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be inter- ...
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... Figure 11-6. Watchdog System Reset During Operation 11.7 Internal Voltage Reference ATmega48A/PA/88A/PA/168A/PA/328/P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...
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... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 11.8.2 Overview ATmega48A/PA/88A/PA/168A/PA/328/P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the coun- ter before the time-out value is reached ...
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... The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 53 ...
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... Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Turn off global interrupt cli ...
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... Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ...
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... Read/Write Initial Value • Bit 7:4: Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. • Bit 3 – WDRF: Watchdog System Reset Flag This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
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... The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 11-2 on page Table 11-2. WDP3 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Watchdog Timer Configuration (1) WDE WDIE Mode 0 0 Stopped 0 1 Interrupt Mode 1 0 ...
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... Table 11-2. WDP3 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Watchdog Timer Prescale Select (Continued) Number of WDT Oscillator WDP2 WDP1 WDP0 512K (524288) cycles 1024K (1048576) cycles Typical Time-out at ...
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... ATmega48A/PA/88A/PA/168A/PA/328/P. For a general explanation of the AVR interrupt han- ...
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... Table 12-1. Reset and Interrupt Vectors in ATmega48A and ATmega48PA (Continued) Vector No. Program Address 24 0x017 25 0x018 26 0x019 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega 48A/48PA is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 ...
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... Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Source Interrupt Definition RESET ...
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... ATmega48A/PA/88A/PA/168A/PA/328/P Reset and Interrupt Vectors Placement in ATmega88A and ATmega88PA IVSEL Reset Address 1 0 0x000 1 1 0x000 0 0 Boot Reset Address 0 1 Boot Reset Address 1. The Boot Reset Address is shown in means unprogrammed while “ ...
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... Reset and Interrupt Vector Addresses in ATmega88A/88PA is: Address Labels Code ; .org 0xC00 0xC00 0xC01 0xC02 ... 0xC19 ; 0xC1A 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx ...
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... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P out SPH,r16 ...
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... ATmega48A/PA/88A/PA/168A/PA/328/P shows reset and Interrupt Vectors placement for the various combina- Reset and Interrupt Vectors Placement in ATmega168A and ATmega168PA IVSEL Reset Address 1 0 0x000 1 1 0x000 ...
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... When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168A/168PA is: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P out SPH,r16 ldi ...
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... ATmega48A/PA/88A/PA/168A/PA/328/P jmp RESET jmp EXT_INT0 jmp EXT_INT1 ... ... jmp SPM_RDY RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx ...
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... ATmega48A/PA/88A/PA/168A/PA/328/P Source Interrupt Definition USART, TX USART, Tx Complete ADC ADC Conversion Complete EE READY EEPROM Ready ANALOG COMP Analog Comparator TWI 2-wire Serial Interface SPM READY Store Program Memory Ready 280 ...
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... When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega328/328P is: Address Labels Code .org 0x0002 0x0002 0x0004 ... 0x0032 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P jmp TIM1_OVF jmp TIM0_COMPA jmp TIM0_COMPB jmp TIM0_OVF jmp ...
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... Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter- mined by the BOOTSZ Fuses. Refer to the section Self-Programming” on page 280 tables, a special write procedure must be followed to change the IVSEL bit: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ...
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... ATmega48A/PA/88A/PA/168A/PA/328/P If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” ...
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... An example of timing of a pin change interrupt is shown in Figure 13-1. Timing of pin change interrupts 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 27. Low level interrupt on INT0 and INT1 is detected asynchro- Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt ...
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... Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre- sponding interrupt mask are set ...
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... Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...
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... Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. • Bit 2 – PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled ...
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... Read/Write Initial Value • Bit 7 – Reserved This bit is an unused bit in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. • Bit 6:0 – PCINT[14:8]: Pin Change Enable Mask 14...8 Each PCINT[14:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin ...
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... Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Functions” on page nate functions. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P and Ground as indicated in CC for a complete list of parameters. Pxn ...
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... To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) Pxn SLEEP ...
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... The maximum and minimum propagation delays are denoted t 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P summarizes the control signals for the pin value. Port Pin Configurations PUD ...
Page 80
... The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P SYSTEM CLK XXX SYNC LATCH ...
Page 81
... If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ... ; Define pull-ups and set outputs high ...
Page 82
... DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P or GND is not recommended, since this may cause excessive currents if the pin is CC (1) PUOExn PUOVxn 1 0 DDOExn ...
Page 83
... Refer to the alternate function description for further details. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are ...
Page 84
... TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Port B Pins Alternate Functions Alternate Functions Chip Clock Oscillator pin 2 ...
Page 85
... PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source. • OC1A/PCINT1 – Port B, Bit 1 OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 85 ...
Page 86
... PVOV DIEOE DIEOV DI AIO Notes: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P and Table 14-5 on page 87 relate the alternate functions of Port B to the overriding Figure 14-5 on page 82. SPI MSTR INPUT and SPI SLAVE OUTPUT consti- Overriding Signals for Alternate Functions in PB7...PB4 PB7/XTAL2/ ...
Page 87
... DI AIO 14.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 14-6. Port Pin 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Overriding Signals for Alternate Functions in PB3...PB0 PB3/MOSI/ PB2/SS/ OC2/PCINT3 OC1B/PCINT2 SPE • MSTR SPE • MSTR PORTB3 • PUD PORTB2 • ...
Page 88
... ADC2/PCINT10 – Port C, Bit 2 PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog power. PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt source. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 88 ...
Page 89
... PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P and Table 14-8 relate the alternate functions of Port C to the overriding signals Figure 14-5 on page 82. Overriding Signals for Alternate Functions in PC6...PC4 PC6/RESET/PCINT14 PC5/SCL/ADC5/PCINT13 RSTDISBL TWEN 1 PORTC5 • ...
Page 90
... DDOV PVOE PVOV DIEOE DIEOV DI AIO 14.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 14-9. Port Pin 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Overriding Signals for Alternate Functions in PC3...PC0 PC3/ADC3/ PC2/ADC2/ PCINT11 PCINT10 ...
Page 91
... Timer/Counter0 Compare Match B. The PD3 pin has to be configured as an output (DDD3 set (one)) to serve this function. The OC2B pin is also the output pin for the PWM mode timer function. PCINT19: Pin Change Interrupt source 19. The PD3 pin can serve as an external interrupt source. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 91 ...
Page 92
... Table 14-10. Overriding Signals for Alternate Functions PD7...PD4 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P and Table 14-11 relate the alternate functions of Port D to the overriding signals Figure 14-5 on page 82. PD7/AIN1 PD6/AIN0/ /PCINT23 OC0A/PCINT22 ...
Page 93
... Table 14-11. Overriding Signals for Alternate Functions in PD3...PD0 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P PD3/OC2B/INT1/ PD2/INT0/ PCINT19 PCINT18 OC2B ENABLE 0 OC2B 0 INT1 ENABLE + INT0 ENABLE + PCINT19 • ...
Page 94
... Initial Value 14.4.6 DDRC – The Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 14.4.7 PINC – The Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial Value 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 (1) (1) – BODS BODSE R R/W R ...
Page 95
... Initial Value 14.4.9 DDRD – The Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 14.4.10 PIND – The Port D Input Pins Address Bit 0x09 (0x29) Read/Write Initial Value Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 PORTD7 PORTD6 PORTD5 R/W R/W R ...
Page 96
... I/O Register and bit locations are listed in the The PRTIM0 bit in enable Timer/Counter0 module. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”Pinout ATmega48A/PA/88A/PA/168A/PA/328/P” on page ”Register Description” on page ”Minimizing Power Consumption” on page 43 Figure 15-1. For the actual 2. CPU 108 ...
Page 97
... Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter- rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Count Clear Control Logic ...
Page 98
... Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk count operations. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”Using the Output Compare Unit” on page 125 ”Timer/Counter0 and Timer/Counter1 Prescalers” on page DATA BUS count ...
Page 99
... The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 101. (”Modes of Operation” on page shows a block diagram of the Output Compare unit. ...
Page 100
... PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin system reset occur, the OC0x Register is reset to “0”. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Figure 15-4 shows a simplified 100 ...
Page 101
... PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See For detailed timing information refer to 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P COMnx1 Waveform COMnx0 D ...
Page 102
... For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Figure 1 2 ...
Page 103
... TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P f clk_I/O = ------------------------------------------------- - f ⋅ ⋅ ...
Page 104
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Table 15-6 on page f OCnxPWM 15-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 109) ...
Page 105
... TOM. There are two cases that give a transition without Compare Match. • OCRnx changes its value from MAX, like in OCn pin value is the same as the result of a down-counting Compare Match. To ensure 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 Table 15-7 on page ...
Page 106
... TCNTn TOVn Figure 15-10 mode and PWM mode, where OCR0A is TOP. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Figure 15-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ...
Page 107
... Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) ...
Page 108
... CTC mode (non-PWM). Table 15-2. COM0A1 Table 15-3 mode. Table 15-3. COM0A1 Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 COM0A1 COM0A0 COM0B1 R/W R/W R Table 15-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode COM0A0 ...
Page 109
... COM0B1 Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. ...
Page 110
... Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 111
... A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Reserved These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • ...
Page 112
... The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Clock Select Bit Description CS01 CS00 ...
Page 113
... Read/Write Initial Value • Bits 7:3 – Reserved These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 114
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 110. Table 15-8, ”Waveform ...
Page 115
... I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”Pinout ATmega48A/PA/88A/PA/168A/PA/328/P” on page ”Register Description” on page ”PRR – Power Reduction Register” on page 46 Figure 16-1. For the actual 2 ...
Page 116
... The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun- ter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Count Clear Control Logic ...
Page 117
... OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 124. The compare match event will also set the Compare Match 248) The Input Capture unit includes a digital filtering unit (Noise The counter reaches the BOTTOM when it becomes 0x0000 ...
Page 118
... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ... ; Set TCNT1 to 0x01FF ...
Page 119
... The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Save global interrupt flag in r18,SREG ...
Page 120
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ...
Page 121
... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P shows a block diagram of the counter and its surroundings. DATA BUS (8-bit) ...
Page 122
... The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P DATA BUS TEMP (8-bit) ICRnH (8-bit) ...
Page 123
... Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 117. ”Accessing 16-bit Registers” (Figure 17-1 on page 143) ...
Page 124
... The double buffering synchronizes the update of the OCR1x Com- pare Register to either TOP or BOTTOM of the counting sequence. The synchronization 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (See Section “16.9” on page shows a block diagram of the Output Compare unit. The small “n” in the register and ...
Page 125
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 117. ”Accessing 16-bit Registers” 125 ...
Page 126
... The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register performed on the next compare match. For compare output actions in the 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Waveform Generator I/O See Section “ ...
Page 127
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Table 16-1 on page 136. For fast PWM mode refer to 126.) ”Timer/Counter Timing Diagrams” on page ...
Page 128
... PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 when OCR1A is set to zero (0x0000) ...
Page 129
... TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ( log TOP ...
Page 130
... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P f clk_I ---------------------------------- - ⋅ ...
Page 131
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg- ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ( log TOP ...
Page 132
... OCR1x Register is updated by the OCR1x Buffer Register, (see 8 and Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P f OCnxPCPWM 16-9). Table on page f clk_I/O ...
Page 133
... Figure 16-9 cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P log R = ---------------------------------- - ...
Page 134
... The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 16-11 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P f OCnxPFCPWM Figure 16-10 clk I/O ...
Page 135
... TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 16-12. Timer/Counter Timing Diagram, no Prescaling (PC and PFC PWM) 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P clk I/O clk Tn ...
Page 136
... When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 16-1. COM1A1/COM1B1 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P shows the same timing data, but with the prescaler enabled. clk I/O clk Tn ...
Page 137
... Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast Compare Output Mode, Fast PWM ...
Page 138
... When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) WGM10 Timer/Counter Mode of ...
Page 139
... A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Figure 16-11. Clock Select Bit Description CS11 ...
Page 140
... The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 ...
Page 141
... TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 7, 6 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”Accessing 16-bit Registers” on page 7 ...
Page 142
... ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 4, 3 – Reserved These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero. • Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B) ...
Page 143
... The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization ...
Page 144
... An external clock source can not be prescaled. Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1 PSRSYNC Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O clk ...
Page 145
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 TSM – ...
Page 146
... The PRTIM2 bit in enable Timer/Counter2 module. Figure 18-1. 8-bit Timer/Counter Block Diagram 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”Pinout ATmega48A/PA/88A/PA/168A/PA/328/P” on page ”Register Description” on page ”Minimizing Power Consumption” on page 43 Count Clear Control Logic ...
Page 147
... Prescaler” on page 18.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 18-2 on page 148 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 ”Output Compare Unit” on page 148 Table 18-1 are also used extensively throughout the section. Definitions The counter reaches the BOTTOM when it becomes zero (0x00) ...
Page 148
... WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 18-3 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P DATA BUS count clear TCNTn ...
Page 149
... Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P DATA BUS OCRnx = (8-bit Comparator ) ...
Page 150
... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the out- put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Waveform Generator clk I/O ” ...
Page 151
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Table 18-5 on page ”Compare Match Output Unit” on page ”Timer/Counter Timing Diagrams” on page 161 ...
Page 152
... This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 ...
Page 153
... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Figure 18-6. The TCNT2 value is in the timing diagram shown as a his- ...
Page 154
... In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 18-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating when OCR2A is set to zero ...
Page 155
... MAX value in all modes other than phase correct PWM mode. Figure 18-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 18-9 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P f OCnxPCPWM Figure 18-7 contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled ...
Page 156
... OCRnx OCFnx Figure 18-11 Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P I/O Tn /8) I/O MAX - 1 shows the setting of OCF2A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode ...
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... The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Enable interrupts, if needed. 157 ...
Page 158
... The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ) again becomes active, TCNT2 will read as the previous value (before entering sleep) clk I/O ...
Page 159
... For Timer/Counter2, the possible prescaled selections are: clk clk /128, clk T2S Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P /256, and clk /1024. Additionally, clk T2S T2S /8, clk /32, clk ...
Page 160
... CTC mode (non-PWM). Table 18-2. COM2A1 Table 18-3 mode. Table 18-3. COM2A1 Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 COM2A1 COM2A0 COM2B1 R/W R/W R Table 18-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode COM2A0 ...
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... Table 18-6. COM2B1 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM2A0 Description 0 Normal port operation, OC2A disconnected. WGM22 = 0: Normal Port Operation, OC2A Disconnected. ...
Page 162
... Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting ...
Page 163
... A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Reserved These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • ...
Page 164
... The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2B pin. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Clock Select Bit Description CS21 CS20 ...
Page 165
... When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter- rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 – ...
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... A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 – ...
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... If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the chronization Mode” on page 145 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 TSM – ...
Page 168
... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega48A/PA/88A/PA/168A/PA/328/P and peripheral devices or between several AVR devices. The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 206. The PRSPI bit in module. 8271D– ...
Page 169
... Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) DIVIDER /2/4/8/16/32/64/128 1 ...
Page 170
... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Table 19-1 on page 170. For more details on automatic port overrides, refer to 82. ...
Page 171
... C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) ...
Page 172
... Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) DDR_SPI,r17 out ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret ; Wait for reception complete ...
Page 173
... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum- marizing Table 19-2. SPI Mode 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Figure 19-4 on page 174. Data bits are shifted out and latched in on opposite edges of Table 19-3 on page 175 and ...
Page 174
... Figure 19-3. SPI Transfer Format with CPHA = 0 Figure 19-4. SPI Transfer Format with CPHA = 1 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 Bit 5 LSB first (DORD = 1) ...
Page 175
... Table 19-3. • Bit 2 – CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to functionality is summarized below: Table 19-4. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 SPIE SPE DORD ...
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... WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. • Bit [5:1] – Reserved These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit ...
Page 177
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 ...
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... Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”Minimizing Power Consumption” on page 43 Figure 20-1 on page 179. CPU ...
Page 179
... UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) UBRRn [H:L] BAUD RATE GENERATOR ...
Page 180
... Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P shows a block diagram of the clock generation logic. UBRRn foscn ...
Page 181
... For the Transmitter, there are no downsides. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P contains equations for calculating the baud rate (in bits per second) and for calculat- Equations for Calculating Baud Rate Register Setting ...
Page 182
... ATmega48A/PA/88A/PA/168A/PA/328/P Figure 20-2 for details. depends on the stability of the system clock source therefore recommended to osc UCPOL = 1 ...
Page 183
... The relation between the parity bit and data bits is as follows used, the parity bit is located between the last data bit and first stop bit of a serial frame. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P illustrates the possible combinations of the frame formats. Bits inside brackets are (IDLE Start bit, always low ...
Page 184
... The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 184 ...
Page 185
... Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If syn- 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Set baud rate out ...
Page 186
... UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Wait for empty transmit buffer in r16, UCSRnA ...
Page 187
... USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1)(2) ; Wait for empty transmit buffer in r16, UCSRnA ...
Page 188
... Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 188 ...
Page 189
... FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Wait for data to be received in r16, UCSRnA ...
Page 190
... Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) ; Wait for data to be received in r16, UCSRnA sbrs r16, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA ...
Page 191
... The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Par- ity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P ”Parity Bit Calculation” on page 183 and ” ...
Page 192
... Receiver. The asynchronous reception operational range depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P (1) in r16, UCSRnA sbrs r16, RXCn ...
Page 193
... If two or all three samples have high levels, the received bit is registered logic 1. If two or all three samples have low levels, the received bit is registered logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P RxD IDLE Sample ...
Page 194
... The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. Table slow 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P shows the sampling of the stop bit and the earliest possible beginning RxD Sample (U2X = Sample (U2X = 1) ...
Page 195
... CPU system with multiple MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P and Table 20-3 on page 195 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode ...
Page 196
... For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRRn settings in which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P Table . UBRRn values 196 ...
Page 197
... Max. 62.5kbps Note: 1. UBRRn = 0, Error = 0.0% 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 194). The error values are calculated using the following equation: BaudRate ⎛ Error[%] = ------------------------------------------------- - 1 ⎝ 1.8432MHz osc U2Xn = 1 U2Xn = 0 Error UBRRn Error ...
Page 198
... Max. 230.4kbps 460.8kbps 1. UBRRn = 0, Error = 0.0% 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 4.0000MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 16 2.1% 34 0.0% 12 0.2% 25 0.0% 8 -3. ...
Page 199
... Max. 0.5Mbps 1. UBRRn = 0, Error = 0.0% 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328/P 11.0592 f = osc U2Xn = 0 Error UBRRn Error UBRRn -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – ...
Page 200
... Max. 1Mbps 1. UBRRn = 0, Error = 0.0% 8271D–AVR–05/11 ATmega48A/PA/88A/PA/168A/PA/328 18.4320MHz osc U2Xn = 0 Error UBRRn Error UBRRn 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – ...