ATmega48A Atmel Corporation, ATmega48A Datasheet - Page 49

• Manufacturer Part Number: ATmega48A
• Manufacturer: Atmel Corporation

Specifications of ATmega48A

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.3
8271D–AVR–05/11
Power-on Reset
Figure 11-1. Reset Logic
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in
V
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V
Figure 11-2. MCU Start-up, RESET Tied to V
CC
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
INTERNAL
TIME-OUT
BODLEVEL [2..0]
RSTDISBL
CC
RESET
RESET
V
decreases below the detection level.
CC
”System and Reset Characteristics” on page
Pull-up Resistor
FILTER
SPIKE
ATmega48A/PA/88A/PA/168A/PA/328/P
V
V
POT
RST
CC
t
TOUT
CKSEL[3:0]
rise. The RESET signal is activated again, without any delay,
Power-on Reset
Reset Circuit
SUT[1:0]
Brown-out
Watchdog
Oscillator
Generator
Circuit
Clock
CK
CC
Register (MCUSR)
MCU Status
DATA BUS
Delay Counters
324. The POR is activated whenever
TIMEOUT
49