ATmega645P Atmel Corporation, ATmega645P Datasheet - Page 66
ATmega645P
Manufacturer Part Number
ATmega645P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega645P
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.2.4
13.2.5
13.2.6
8285D–AVR–06/11
PCMSK3 – Pin Change Mask Register 3
PCMSK2 – Pin Change Mask Register 2
PCMSK1 – Pin Change Mask Register 1
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
• Bit 4 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
Note:
• Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30:24
Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT30:24 is set and the PCIE3 bit in EIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT30:24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Note:
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in EIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
Bit
(0x6D)
Read/Write
Initial Value
Bit
(0x73)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
1. PCMSK3 and PCMSK2 are only present in ATmega3250A/3250PA/6450A/6450P.
1. PCMSK3 and PCMSK2 are only present in ATmega3250A/3250PA/6450A/6450P.
PCINT23
R/W
PCINT15
7
0
R
7
0
–
R/W
7
0
PCINT22
PCINT30
R/W
R/W
PCINT14
6
0
6
0
R/W
(1)
(1)
6
0
PCINT21
PCINT29
R/W
R/W
PCINT13
5
0
5
0
R/W
5
0
PCINT20
PCINT28
R/W
PCINT12
R/W
4
0
4
0
R/W
4
0
PCINT19
PCINT27
PCINT11
R/W
R/W
3
0
R/W
3
0
3
0
PCINT18
PCINT26
PCINT10
R/W
R/W
2
0
R/W
2
0
2
0
PCINT17
PCINT25
PCINT9
R/W
R/W
R/W
1
0
1
0
1
0
PCINT16
PCINT24
PCINT8
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK2
PCMSK3
PCMSK1
66
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