ATmega8 Atmel Corporation, ATmega8 Datasheet - Page 100

• Manufacturer Part Number: ATmega8
• Manufacturer: Atmel Corporation

Specifications of ATmega8

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Input Capture Register
1 – ICR1H and ICR1L
Timer/Counter
Interrupt Mask
Register – TIMSK
100
ATmega8(L)
(1)
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare Interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes
are written simultaneously when the CPU writes to these registers, the access is performed
using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the
other 16-bit registers.
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Cap-
ture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt
Vector (see
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(see
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
“Interrupts” on page
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
See “Accessing 16-bit Registers” on page 77.
described in this section. The remaining bits are described in their respective timer sections
“Interrupts” on page
OCIE2
R/W
R/W
7
0
7
0
See “Accessing 16-bit Registers” on page 77.
“Interrupts” on page
“Interrupts” on page
TOIE2
R/W
R/W
6
0
6
0
46) is executed when the TOV1 Flag, located in TIFR, is set.
TICIE1
R/W
R/W
5
0
5
0
46) is executed when the ICF1 Flag, located in TIFR, is set.
OCIE1A
R/W
R/W
0
0
4
4
ICR1[15:8]
ICR1[7:0]
46) is executed when the OCF1A Flag, located in
46) is executed when the OCF1B Flag, located in
OCIE1B
R/W
R/W
3
0
3
0
TOIE1
R/W
R/W
2
0
2
0
R/W
R
1
0
1
–
0
TOIE0
R/W
R/W
0
0
0
0
ICR1H
ICR1L
TIMSK
2486Z–AVR–02/11