ATtiny2313 Atmel Corporation, ATtiny2313 Datasheet - Page 33

• Manufacturer Part Number: ATtiny2313
• Manufacturer: Atmel Corporation

Specifications of ATtiny2313

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 18
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

System Control
and Reset
Resetting the AVR
Reset Sources
2543L–AVR–08/10
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in
parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
The ATtiny2313 has four sources of reset:
•
•
•
•
Figure 14. Reset Logic
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (V
External Reset. The MCU is reset when a low level is present on the RESET pin for longer
than the minimum pulse length.
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires, the Watchdog
is enabled, and Watchdog Interrupt is disabled.
Brown-out Reset. The MCU is reset when the supply voltage V
Reset threshold (V
BODLEVEL [2..0]
POT
).
BOT
Pull-up Resistor
) and the Brown-out Detector is enabled.
FILTER
SPIKE
Figure 14
CKSEL[3:0]
Power-on Reset
Reset Circuit
SUT[1:0]
Brown-out
Watchdog
Oscillator
Generator
Circuit
Clock
shows the reset logic.
CK
Register (MCUSR)
MCU Status
DATA BUS
Delay Counters
“Clock Sources” on page
Table 15
CC
TIMEOUT
is below the Brown-out
defines the electrical
23.
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