ATtiny24 Atmel Corporation, ATtiny24 Datasheet - Page 113

• Manufacturer Part Number: ATtiny24
• Manufacturer: Atmel Corporation

Specifications of ATtiny24

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.11.7
12.11.8
8006K–AVR–10/10
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter Interrupt Mask Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved in the ATtiny24/44/84 and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 66.) is executed when the
ICF1 Flag, located in TIFR1, is set.
• Bits 4:3 – Res: Reserved Bits
These bits are reserved in the ATtiny24/44/84 and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(see
Bit
0x25 (0x45)
0x24 (0x44)
Read/Write
Initial Value
Bit
0x0C (0x2C)
Read/Write
Initial Value
“Interrupts” on page
“Accessing 16-bit Registers” on page
R/W
R
7
0
7
–
0
“Interrupts” on page
“Interrupts” on page
R/W
48) is executed when the TOV1 flag, located in TIFR1, is set.
R
6
0
6
–
0
R/W
ICIE1
R/W
5
0
5
0
R/W
48) is executed when the OCF1B flag, located in
48) is executed when the OCF1A flag, located in
4
0
R
4
–
0
ICR1[15:8]
ICR1[7:0]
105.
R/W
3
0
R
3
–
0
OCIE1B
R/W
R/W
2
0
2
0
ATtiny24/44/84
OCIE1A
R/W
R/W
1
0
1
0
R/W
TOIE1
R/W
0
0
0
0
ICR1H
TIMSK1
ICR1L
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