ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 2

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ATtiny28L

Manufacturer Part Number
ATtiny28L
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny28L

Flash (kbytes)
2 Kbytes
Pin Count
28
Max. Operating Frequency
4 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
11
Ext Interrupts
10
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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Description
Block Diagram
2
ATtiny28L/V
The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-
tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves
throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize
power consumption versus processing speed. The AVR core combines a rich instruction
set with 32 general-purpose working registers. All the 32 registers are directly con-
nected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architec-
ture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
Figure 1. The ATtiny28 Block Diagram
The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O
lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an
8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with
internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops
the CPU while allowing the timer/counter and interrupt system to continue functioning.
The Power-down mode saves the register contents but freezes the oscillator, disabling
all other chip functions until the next interrupt or hardware reset. The wake-up or inter-
GND
VCC
PROGRAMMING
INSTRUCTION
INSTRUCTION
CONTROL
PROGRAM
COUNTER
PROGRAM
REGISTER
DECODER
LINES
FLASH
LOGIC
DATA REGISTER
PORTB
PORTB
HARDWARE
REGISTERS
REGISTER
GENERAL
PURPOSE
POINTER
STATUS
STACK
STACK
ALU
Z
8-BIT DATA BUS
DATA REGISTER
PORTD
MCU CONTROL
OSCILLATOR
WATCHDOG
INTERRUPT
COUNTER
REGISTER
INTERNAL
TIMER/
TIMER
UNIT
PORTD
XTAL1
REG. PORTD
DATA DIR
OSCILLATOR
TIMING AND
CONTROL
XTAL2
DATA REGISTER
CALIBRATED
OSCILLATOR
PORTA
INTERNAL
MODULATOR
PORTA
HARDWARE
PORTA CONTROL
REGISTER
1062F–AVR–07/06
RESET

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