ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 24
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ATtiny28L
Manufacturer Part Number
ATtiny28L
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny28L
Flash (kbytes)
2 Kbytes
Pin Count
28
Max. Operating Frequency
4 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
11
Ext Interrupts
10
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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24
ATtiny28L/V
enable bit, INT0 in GIMSK is set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured
as level interrupt.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and always reads as zero.
• Bit 4 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. TOV0 is
cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 in ICR and TOV0
are set (one), the Timer/Counter0 Overflow interrupt is executed.
• Bit 3..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny28 and always read as zero.
Note:
1. One should not try to use the SBI (Set Bit in I/O Register) instruction to clear individ-
ual flags in the Register. This will result in clearing all the flags in the register,
because the register is first read, then modified and finally written, thus writing ones
to all set flags. Using the CBI (Clear Bit in I/O Register) instruction on IFR will result in
clearing all bits apart from the specified bit.
1062F–AVR–07/06