ATtiny9 Atmel Corporation, ATtiny9 Datasheet - Page 3
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ATtiny9
Manufacturer Part Number
ATtiny9
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny9
Flash (kbytes)
1 Kbytes
Pin Count
6
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
1
Hardware Qtouch Acquisition
No
Max I/o Pins
4
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATtiny9-MAHR
Manufacturer:
ST
Quantity:
101
Company:
Part Number:
ATtiny9-TS8R
Manufacturer:
Atmel
Quantity:
482
Company:
Part Number:
ATtiny9-TSHR
Manufacturer:
RFMD
Quantity:
5 000
Company:
Part Number:
ATtiny9TSHR
Manufacturer:
ATMEL
Quantity:
5 399
2. Overview
8127E–AVR–11/11
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer
to optimize power consumption versus processing speed.
Figure 2-1.
The AVR core combines a rich instruction set with 16 general purpose working registers and
system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock cycle.
The resulting architecture is compact and code efficient while achieving throughputs up to ten
times faster than conventional CISC microcontrollers.
PROGRAMMING
INSTRUCTION
INSTRUCTION
INTERFACE
PROGRAM
REGISTER
DECODER
CONTROL
DATA REGISTER
FLASH
LOGIC
LINES
ISP
PORT B
Block Diagram
V
DRIVERS
PORT B
CC
PB3:0
REG. PORT B
REGISTERS
DIRECTION
PROGRAM
REGISTER
COUNTER
PURPOSE
GENERAL
POINTER
STATUS
STACK
SRAM
ALU
X
Y
Z
GND
8-BIT DATA BUS
COMPARATOR
MCU STATUS
OSCILLATOR
RESET FLAG
WATCHDOG
INTERRUPT
COUNTER0
REGISTER
REGISTER
INTERNAL
ANALOG
TIMER/
TIMER
UNIT
ATtiny4/5/9/10
RESET
OSCILLATOR
CALIBRATED
TIMING AND
CONTROL
ADC
3