ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 116

• Manufacturer Part Number: ATxmega128B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.7.2
8291A–AVR–10/11
WINCTRL – Window Mode Control register
Table 10-1.
• Bit 1 – ENABLE: Enable
This bit enables the WDT. Clearing this bit disables the watchdog timer.
In order to change this bit, the CEN bit in
to one at the same time. This bit is protected by the configuration change protection mechanism,
For a detailed description, refer to
• Bit 0 – CEN: Change Enable
This bit enables the ability to change the configuration of the
115. When writing a new value to this register, this bit must be written to one at the same time for
the changes to take effect. This bit is protected by the configuration change protection mecha-
nism. For a detailed description, refer to
• Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 5:2 – WPER[3:0]: Window Mode Timeout Period
These bits determine the closed window period as a number of 1kHz ULP oscillator cycles in
window mode operation. The typical different closed window periods are found in
The initial values of these bits are set by the watchdog window timeout period (WDWP) fuses,
and are loaded at power-on. In normal mode these bits are not in use.
Bit
+0x01
Read/Write
(unlocked)
Read/Write
(locked)
Initial Value
(x = fuse)
PER[3:0]
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Watchdog timeout periods (Continued).
R
R
7
–
0
R
R
6
–
0
Group Configuration
R/W
512CLK
R
X
5
1KCLK
2KCLK
4KCLK
8KCLK
”Configuration Change Protection” on page
”Configuration Change Protection” on page
”CTRL – Control register” on page 115
R/W
R
4
X
WPER[3:0]
R/W
R
X
3
Atmel AVR XMEGA B
R/W
”CTRL – Control register” on page
2
R
X
Typical Timeout Periods
WEN
R/W
R/W
X
1
Reserved
Reserved
Reserved
Reserved
Reserved
0.512s
1.0s
2.0s
4.0s
8.0s
12.
WCEN
R/W
R/W
must be written
0
0
Table
12.
WINCTRL
10-2.
116