ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 288

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.13 Register Summary - EBI
24.14 Register Summary - EBI Chip Select
8077H–AVR–12/09
Address
Address
+0x00
+0x01
+0x02
+0x03
+0x0A
+0x0B
+0x0C
+0x0D
+0x0E
+0x1C
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x07
+0x08
+0x09
+0x0F
+0x10
+0x14
+0x18
Name
CTRLA
CTRLB
BASEADDRL
BASEADDRH
Name
CTRL
SDRAMCTRLA
Reserved
Reserved
REFRESHL
REFRESHH
INITDLYL
INITDLYH
SDRAMCTRLB
SDRAMCTRLC
Reserved
Reserved
CS0
CS1
CS2
CS3
Reserved
Reserved
Reserved
Reserved
(SRAM)
(SDRAM)
Bit 7
SDINITDONE
-
-
-
-
-
-
-
-
-
-
-
SDDATAW[1:0]
Bit 7
MRDLY[1:0]
RWDLY[1:0]
-
-
Chip Select Base Address Low Byte
Bit 6
-
-
-
-
-
-
-
-
-
-
-
Bit 6
-
-
Bit 5
-
-
-
-
-
-
-
-
-
-
Bit 5
LPCMODE[1:0]
-
-
ROWCYCDLY[[2:0]
SDRAM Initialization Time Low Byte
SDRAM Refresh Period Low Byte
ESRDLY[2:0]
Chip Select Base Address High Byte
Chip Select 0 Offset Address
Chip Select 1 Offset Address
Chip Select 2 Offset Address
Chip Select 3 Offset Address
Bit 4
ASIZE[4:0]
-
-
-
-
-
-
-
-
-
-
Bit 4
-
-
SDRAM Initialization Time High Byte
SDCAS
Bit 3
Bit 3
-
-
-
-
-
-
-
-
-
SRMODE[1:0]
-
-
-
SDROW
Bit 2
SDSREN
Bit 2
-
-
-
-
-
-
-
-
-
-
ROWCOLDLY[2:0]
RPDLY[2:0]
SDRAM Refresh Period High
SRWS[2:0]
Bit 1
Bit 1
-
-
-
-
-
-
-
-
-
IFMODE[1:0]
SDCOL[1:0]
SDMODE[1:0]
MODE[1:0]
XMEGA A
Bit 0
Bit 0
-
-
-
-
-
-
-
-
-
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