ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 363

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.3
30.4
30.4.1
30.4.2
30.4.3
30.4.4
30.5
8077H–AVR–12/09
NVM Controller
NVM Commands
NVM Controller Busy
Action Triggered Commands
NVM Read Triggered commands
NVM Write Triggered Commands
CCP Write/Execute Protection
For both self-programming and external programming it is possible to run an automatic CRC
check on the Flash or a section of the Flash to verify its content.
The device can be locked to prevent read and/or write of the NVM. There are separate lock bits
for external programming access, and self-programming access to the Boot Loader Section,
Application Section and Application Table Section.
All access to the Non Volatile Memories is done through the NVM Controller. This controls all
NVM timing and access privileges, and hold the status of the NVM. This is the common NVM
interface for both the external programming and self-programming. For more details on the NVM
Controller refer to
The NVM Controller has a set of commands that decide the task to perform on the NVM. This is
issued to the NVM Controller by writing the selected command to the NVM Command Register.
In addition data and addresses must be read/written from/to the NVM Data and Address regis-
ters for memory read/write operations.
When a selected command is loaded and address and data is setup for the operation, each
command has a trigger that will start the operation. Bases on the triggers, there are three main
types of commands.
Action triggered commands are triggered when the Command Execute (CMDEX) bit in the NVM
Control Register A (CTRLA) is written. Action triggered commands typically are used for opera-
tions which do not read or write the NVM such as the CRC check.
NVM read triggered commands are triggered when the NVM memory is read, and this is typically
used for NVM read operations.
NVM Write Triggered commands are triggered when the NVN is written, and this is typically
used for NVM write operations.
Most command triggers are protected from accidental modification/execution during self-pro-
gramming. This is done using the Configuration Change Protection (CCP) feature which
requires a special write or execute sequence in order to change a bit or execute an instruction.
For details on the CCP, refer to
When the NVM Controller is busy performing an operation, the Busy flag in the NVM Status
Register is set and the following registers are blocked for write access:
• NVM Command Register
• NVM Control A Register
• NVM Control B Register
• NVM Address registers
”Register Description” on page
”Configuration Change Protection” on page 12
385.
XMEGA A
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