SAM3S1A Atmel Corporation, SAM3S1A Datasheet
SAM3S1A
Specifications of SAM3S1A
Related parts for SAM3S1A
SAM3S1A Summary of contents
Page 1
Features • Core ® ® – ARM Cortex -M3 revision 2.0 running MHz – Memory Protection Unit (MPU) ® – Thumb -2 instruction set • Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) • ...
Page 2
... Kbytes SAM3S2B 32 Kbytes single plane 128 Kbytes SAM3S2A 32 Kbytes single plane 64 Kbytes SAM3S1C 16 Kbytes single plane 64 Kbytes SAM3S1B 16 Kbytes single plane 64 Kbytes SAM3S1A 16 Kbytes single plane Note: 1. Full Modem support on USART1. SAM3S Summary 2 Timer Counter UART/ Channels GPIOs USARTs ADC ( 2 ...
Page 3
SAM3S Block Diagram Figure 2-1. SAM3S 100-pin Version Block Diagram System Controller T ST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M 3-20 MHz XIN Osc. X OUT SUPC XIN32 OSC 32k X OUT32 RC 32k ERASE 8 GPBREG RTT ...
Page 4
Figure 2-2. SAM3S 64-pin Version Block Diagram System Controller T ST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M 3-20 MHz XIN Osc. XOUT SUPC XIN32 OSC 32K XOUT32 RC 32k ERASE 8 GPBREG RTT VDDIO RTC VDDCORE POR VDDPLL RSTC ...
Page 5
Figure 2-3. SAM3S 48-pin Version Block Diagram System Controller TST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M XIN 3-20 MHz XOUT Osc. SUPC XIN32 OSC 32K XOUT32 RC 32k ERASE 8 GPBREG RTT VDDIO RTC VDDCORE POR VDDPLL RSTC WDT ...
Page 6
Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function Peripherals I/O Lines and USB transceiver VDDIO Power Supply Voltage Regulator Input, ADC, DAC and VDDIN Analog Comparator Power Supply VDDOUT Voltage Regulator Output VDDPLL Oscillator and ...
Page 7
Table 3-1. Signal Description List (Continued) Signal Name Function URXDx UART Receive Data UTXDx UART Transmit Data PA0 - PA31 Parallel IO Controller A PB0 - PB14 Parallel IO Controller B PC0 - PC31 Parallel IO Controller C PIODC0-PIODC7 Parallel ...
Page 8
Table 3-1. Signal Description List (Continued) Signal Name Function TD SSC Transmit Data RD SSC Receive Data TK SSC Transmit Clock RK SSC Receive Clock TF SSC Transmit Frame Sync RF SSC Receive Frame Sync TCLKx TC Channel x External ...
Page 9
Table 3-1. Signal Description List (Continued) Signal Name Function PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK Programming Clock PGMNCMD Programming Command DDM USB Full Speed Data - DDP ...
Page 10
Package and Pinout 4.1 SAM3S4/2/1C Package and Pinout Figure 4-2 4.1.1 100-lead LQFP Package Outline Figure 4-1. 4.1.2 100-ball LFBGA Package Outline The 100-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimen- sions ...
Page 11
LQFP Pinout Table 4-1. 100-lead LQFP SAM3S4/2/1C Pinout 1 ADVREF 2 GND 3 PB0/AD4 4 PC29/AD13 5 PB1/AD5 6 PC30/AD14 7 PB2/AD6 8 PC31 9 PB3/AD7 10 VDDIN 11 VDDOUT 12 PA17/PGMD5/AD0 13 PC26 14 PA18/PGMD6/AD1 15 PA21/PGMD9/AD8 ...
Page 12
LFBGA Pinout Table 4-2. 100-ball LFBGA SAM3S4/2/1C Pinout A1 PB1/AD5 C6 A2 PC29 C7 A3 VDDIO C8 A4 PB9/PGMCK/XIN C9 A5 PB8/XOUT C10 A6 PB13/DAC0 D1 A7 DDP/PB11 D2 A8 DDM/PB10 D3 A9 TMS/SWDIO/PB6 D4 A10 JTAGSEL D5 ...
Page 13
SAM3S4/2/1B Package and Pinout Figure 4-3. Figure 4-4. 6500CS–ATARM–24-Jan-11 Orientation of the 64-pad QFN Package TOP VIEW Orientation of the 64-lead LQFP Package SAM3S Summary ...
Page 14
LQFP and QFN Pinout 64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S products have new functionalities shown in italic in Table 4-3. 64-pin SAM3S4/2/1B Pinout 1 ADVREF 17 2 GND 18 3 PB0/AD4 ...
Page 15
SAM3S4/2/1A Package and Pinout Figure 4-5. Figure 4-6. 6500CS–ATARM–24-Jan-11 Orientation of the 48-pad QFN Package TOP VIEW Orientation of the 48-lead LQFP Package SAM3S Summary ...
Page 16
LQFP and QFN Pinout Table 4-4. 48-pin SAM3S4/2/1A Pinout 1 ADVREF 13 2 GND 14 3 PB0/AD4 15 4 PB1/AD5 16 5 PB2/AD6 17 6 PB3/AD7 18 7 VDDIN 19 8 VDDOUT 20 PA17/PGMD5 AD0 PA18/PGMD6/ ...
Page 17
Power Considerations 5.1 Power Supplies The SAM3S product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V and 1.95V. • VDDIO pins: Power the Peripherals ...
Page 18
Figure 5-1. Note: Figure 5-2. Note: Figure 5-3 Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO ...
Page 19
Figure 5-3. 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency ...
Page 20
WKUPEN0-15 pins (level transition, configurable debouncing) • Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a ...
Page 21
Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set off sep- arately and wake up sources can be individually configured. of the configurations of the ...
Page 22
Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they ...
Page 23
Fast Startup The device allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs ...
Page 24
Input/Output Lines The SAM3S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be ...
Page 25
Table 6-1. System I/O Configuration Pin List. SYSTEM_IO Default function bit number after reset 12 ERASE 10 DDM 11 DDP 7 TCK/SWCLK 6 TMS/SWDIO 5 TDO/TRACESWO 4 TDI - PA7 - PA8 - PB9 - PB8 Notes PB12 ...
Page 26
Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it ...
Page 27
Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit • Harvard processor architecture enabling simultaneous instruction fetch with data load/store • Three-stage pipeline • Single ...
Page 28
Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or ...
Page 29
Table 7-4. Instance Name UART0 USART1 USART0 ADC SSC HSMCI PIOA 7.7 Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in ...
Page 30
Product Mapping Figure 8-1. SAM3S Product Mapping Code 0x00000000 Boot Memory 0x00400000 1 MByte 1 MByte Internal Flash 0x00800000 bit band bit band Internal ROM 0x00C00000 Reserved 0x1FFFFFFF External RAM 0x60000000 SMC Chip Select 0 0x61000000 SMC Chip Select ...
Page 31
Memories 9.1 Embedded Memories 9.1.1 Internal SRAM The ATSAM3S4 product (256-Kbyte internal Flash version) embeds a total of 48 Kbytes high- speed SRAM. The ATSAM3S2 product (128-Kbyte internal Flash version) embeds a total of 32 Kbytes high- speed SRAM. ...
Page 32
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 9.1.3.4 Flash Speed The user needs to set the number of wait states depending on the frequency ...
Page 33
Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program- ming with market-standard industrial programmers. The FFPI supports read, ...
Page 34
Asynchronous read in Page Mode supported ( 32-byte page size) • Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation ...
Page 35
System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc... See the system controller block diagram in Figure 10-1. System ...
Page 36
System Controller and Peripherals Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3S embeds three features to monitor, ...
Page 37
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the soft- ware-programmable brownout detector allows detection of either a battery discharge ...
Page 38
Figure 10-2. Clock Generator Block Diagram 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock, HCLK • the Free running processor clock, FCLK • the Cortex SysTick ...
Page 39
Figure 10-3. SAM3S Power Management Controller Block Diagram SLCK MAINCK PLLACK PLLBCK The SysTick calibration value is fixed at 8000 which allows the generation of a time base with SystTick clock at 8 MHz (max HCLK/8 = ...
Page 40
... Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. 10.13 Chip Identification • Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. ATSAM3S4A (Rev A) ATSAM3S2A (Rev A) ATSAM3S1A (Rev A) ATSAM3S4B (Rev A) ATSAM3S2B (Rev A) ATSAM3S1B (Rev A) ATSAM3S4C (Rev A) ATSAM3S2C (Rev A) ATSAM3S1C (Rev A) • ...
Page 41
UART • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun ...
Page 42
Peripherals 11.1 Peripheral Identifiers Table 11-1 the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 11-1. Peripheral Identifiers Instance ID Instance Name ...
Page 43
Peripheral Signal Multiplexing on I/O Lines The SAM3S product features 2 PIO controllers on 48-pin and 64-pin versions (PIOA, PIOB PIO controllers on the 100-pin version, (PIOA, PIOB, PIOC), that multiplex the I/O lines of the peripheral ...
Page 44
PIO Controller A Multiplexing Table 11-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B PA0 PWMH0 TIOA0 PA1 PWMH1 TIOB0 PA2 PWMH2 SCK0 PA3 TWD0 NPCS3 PA4 TWCK0 TCLK0 PA5 RXD0 NPCS3 PA6 TXD0 PCK0 ...
Page 45
PIO Controller B Multiplexing Table 11-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B PB0 PWMH0 PB1 PWMH1 PB2 URXD1 PB3 UTXD1 PB4 TWD1 PB5 TWCK1 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PWML1 PB13 ...
Page 46
PIO Controller C Multiplexing Table 11-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A Peripheral B PC0 D0 PC1 D1 PC2 D2 PC3 D3 PC4 D4 PC5 D5 PC6 D6 PC7 D7 PC8 NWE PC9 NANDOE PC10 ...
Page 47
Embedded Peripherals Overview 12.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – ...
Page 48
Universal Synchronous Asynchronous Receiver Transceiver (USART) • Programmable Baud Rate Generator with Fractional Baud rate support • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode ...
Page 49
Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two ...
Page 50
Programmable Fault Input providing an asynchronous protection of outputs • Stepper motor control (2 Channels) 12.8 High Speed Multimedia Card Interface (HSMCI) • 4-bit or 1-bit Interface • Compatibility with MultiMedia Card Specification Version 4.3 • Compatibility with SD ...
Page 51
Programmable gain 12.11 Digital-to-Analog Converter (DAC) • channel 12-bit DAC • mega-samples conversion rate in single channel mode • Flexible conversion range • Multiple trigger sources for each channel • ...
Page 52
Internal signal – external pin – selectable inverter • Interrupt on: – Rising edge, Falling edge, toggle 12.14 Cyclic Redundancy Check Calculation Unit (CRCCU) • 32-bit cyclic redundancy check automatic calculation • CRC calculation between two ...
Page 53
Package Drawings The SAM3S series devices are available in LQFP, QFN and LFBGA packages. Figure 13-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. ...
Page 54
Figure 13-2. 100-ball LFBGA Package Drawing SAM3S Summary 54 6500CS–ATARM–24-Jan-11 ...
Page 55
Figure 13-3. 64- and 48-lead LQFP Package Drawing 6500CS–ATARM–24-Jan-11 SAM3S Summary 55 ...
Page 56
Table 13-1. Symbol θ 1 θ 2 θ aaa bbb ccc ddd SAM3S Summary 56 48-lead LQFP Package Dimensions (in mm) ...
Page 57
Table 13-2. Symbol θ θ θ aaa bbb ccc ddd 6500CS–ATARM–24-Jan-11 64-lead LQFP Package Dimensions (in mm) Millimeter Min Nom – – ...
Page 58
Figure 13-4. 48-pad QFN Package SAM3S Summary 58 6500CS–ATARM–24-Jan-11 ...
Page 59
Table 13-3. Symbol aaa bbb ccc 6500CS–ATARM–24-Jan-11 48-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.050 – 0.65 0.70 0.20 REF ...
Page 60
Figure 13-5. 64-pad QFN Package Drawing SAM3S Summary 60 6500CS–ATARM–24-Jan-11 ...
Page 61
... A ATSAM3S4AA-MU A ATSAM3S2CA-AU A ATSAM3S2CA-CU A ATSAM3S2BA-AU A ATSAM3S2BA-MU A ATSAM3S2AA-AU A ATSAM3S2AA-MU A ATSAM3S1CA-AU A ATSAM3S1CA-CU A ATSAM3S1BA-AU A ATSAM3S1BA-MU A ATSAM3S1AA-AU A ATSAM3S1AA-MU A 6500CS–ATARM–24-Jan-11 Flash (Kbytes) Package (Kbytes) 256 QFP100 256 BGA100 256 QFP64 256 QFN64 256 QFP48 256 QFN48 128 QFP100 128 BGA100 128 QFP64 128 QFN64 ...
Page 62
Revision History Doc. Rev Comments Missing PGMD8 to 15 added to “100-ball LFBGA SAM3S4/2/1C Section 5.7 “Fast Startup” Typo fixed on back page: ‘techincal’ --> ‘technical’. Typos fixed in Section 1. “SAM3S Missing title added to Table 6500CS PLLA input ...
Page 63
SAM3S Summary 63 ...
Page 64
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2011 Atmel Corporation. All rights reserved. Atmel trademarks of Atmel Corporation or its subsidiaries. ARM trademarks of ARM Ltd. Other terms and product names may be trademarks of others. Atmel Europe ...