SAM3S ATMEL [ATMEL Corporation], SAM3S Datasheet
SAM3S
Related parts for SAM3S
SAM3S Summary of contents
Page 1
... LQFP mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm ® , RS-485, SPI, Manchester and Modem Mode AT91SAM ARM-based Flash MCU SAM3S Series Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6500CS–ATARM–24-Jan-11 ...
Page 2
... SAM3S Description Atmel's SAM3S series is a member of a family of Flash microcontrollers based on the high per- formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and Kbytes of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver, a High Speed MCI for ...
Page 3
... SAM3S Block Diagram Figure 2-1. SAM3S 100-pin Version Block Diagram System Controller T ST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M 3-20 MHz XIN Osc. X OUT SUPC XIN32 OSC 32k X OUT32 RC 32k ERASE 8 GPBREG RTT VDDIO RTC VDDCORE POR VDDPLL RSTC NRST WDT SM PIOA / PIOB / PIOC ...
Page 4
... Figure 2-2. SAM3S 64-pin Version Block Diagram System Controller T ST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M 3-20 MHz XIN Osc. XOUT SUPC XIN32 OSC 32K XOUT32 RC 32k ERASE 8 GPBREG RTT VDDIO RTC VDDCORE POR VDDPLL RSTC NRST WDT SM PIOA / PIOB TWCK0 TWD0 TWCK1 TWD1 ...
Page 5
... Figure 2-3. SAM3S 48-pin Version Block Diagram System Controller TST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M XIN 3-20 MHz XOUT Osc. SUPC XIN32 OSC 32K XOUT32 RC 32k ERASE 8 GPBREG RTT VDDIO RTC VDDCORE POR VDDPLL RSTC WDT SM PIOA / PIOB TWCK0 TWD0 TWCK1 TWD1 URXD0 ...
Page 6
... Test Mode Select /Serial Wire Input/Output JTAGSEL JTAG Selection Flash and NVM Configuration Bits Erase ERASE Command NRST Synchronous Microcontroller Reset TST Test Select SAM3S Summary 6 gives details on the signal names classified by peripheral. Type Power Supplies Power Power Power Power Power ...
Page 7
... NAND Flash Logic Output Output High Speed Multimedia Card Interface - HSMCI I/O I/O I/O I/O I/O Input Output Input I/O Input Input Input SAM3S Summary Active Voltage Level reference Comments Reset State: - PIO or System IOs VDDIO - Internal pull-up enabled - Schmitt Trigger enabled VDDIO Low Low Low Low Low ...
Page 8
... TWIx Two-wire Serial Data TWCKx TWIx Two-wire Serial Clock ADC, DAC and Analog Comparator ADVREF Reference AD0 - AD14 Analog Inputs ADTRG ADC Trigger DAC0 - DAC1 Analog output DACTRG DAC Trigger SAM3S Summary 8 Type Synchronous Serial Controller - SSC Output Input I/O I/O I/O I/O Timer/Counter - TC Input I/O I/O ...
Page 9
... Fast Flash Programming Interface - FFPI Input Input I/O Output Output Input Input Input USB Full Speed Device Analog, Digital for restriction on voltage range of Analog Cells. SAM3S Summary Active Voltage Level reference Comments VDDIO High Low VDDIO Low Low Reset State: VDDIO - USB Mode ...
Page 10
... Package and Pinout 4.1 SAM3S4/2/1C Package and Pinout Figure 4-2 4.1.1 100-lead LQFP Package Outline Figure 4-1. 4.1.2 100-ball LFBGA Package Outline The 100-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimen- sions are 1.1 mm. Figure 4-2. SAM3S Summary 10 shows the orientation of the 100-ball LFBGA Package ...
Page 11
... LQFP Pinout Table 4-1. 100-lead LQFP SAM3S4/2/1C Pinout 1 ADVREF 2 GND 3 PB0/AD4 4 PC29/AD13 5 PB1/AD5 6 PC30/AD14 7 PB2/AD6 8 PC31 9 PB3/AD7 10 VDDIN 11 VDDOUT 12 PA17/PGMD5/AD0 13 PC26 14 PA18/PGMD6/AD1 15 PA21/PGMD9/AD8 16 VDDCORE 17 PC27 18 PA19/PGMD7/AD2 19 PC15/AD11 20 PA22/PGMD10/AD9 21 PC13/AD10 22 PA23/PGMD1 23 PC12/AD12 24 PA20/PGMD8/AD3 25 PC0 6500CS–ATARM–24-Jan-11 26 GND 51 27 VDDIO 52 28 ...
Page 12
... LFBGA Pinout Table 4-2. 100-ball LFBGA SAM3S4/2/1C Pinout A1 PB1/AD5 C6 A2 PC29 C7 A3 VDDIO C8 A4 PB9/PGMCK/XIN C9 A5 PB8/XOUT C10 A6 PB13/DAC0 D1 A7 DDP/PB11 D2 A8 DDM/PB10 D3 A9 TMS/SWDIO/PB6 D4 A10 JTAGSEL D5 B1 PC30 D6 B2 ADVREF D7 B3 GNDANA D8 B4 PB14/DAC1 D9 B5 PC21 D10 B6 PC20 E1 B7 PA31 ...
Page 13
... SAM3S4/2/1B Package and Pinout Figure 4-3. Figure 4-4. 6500CS–ATARM–24-Jan-11 Orientation of the 64-pad QFN Package TOP VIEW Orientation of the 64-lead LQFP Package SAM3S Summary ...
Page 14
... LQFP and QFN Pinout 64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S products have new functionalities shown in italic in Table 4-3. 64-pin SAM3S4/2/1B Pinout 1 ADVREF 17 2 GND 18 3 PB0/AD4 19 4 PB1/AD5 20 5 PB2/AD6 21 6 PB3/AD7 22 7 VDDIN ...
Page 15
... SAM3S4/2/1A Package and Pinout Figure 4-5. Figure 4-6. 6500CS–ATARM–24-Jan-11 Orientation of the 48-pad QFN Package TOP VIEW Orientation of the 48-lead LQFP Package SAM3S Summary ...
Page 16
... LQFP and QFN Pinout Table 4-4. 48-pin SAM3S4/2/1A Pinout 1 ADVREF 13 2 GND 14 3 PB0/AD4 15 4 PB1/AD5 16 5 PB2/AD6 17 6 PB3/AD7 18 7 VDDIN 19 8 VDDOUT 20 PA17/PGMD5 AD0 PA18/PGMD6 AD1 PA19/PGMD7 AD2 12 PA20/AD3 24 Note: The bottom pad of the QFN package must be connected to ground. ...
Page 17
... Voltage Regulator The SAM3S embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is intended to supply the internal core of SAM3S. It features two different operating modes: • In Normal mode, the voltage regulator consumes less than 700 µA static current and draws output current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait Mode quiescent current is only 7 µ ...
Page 18
... Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake-up of the system can be from a push button or any signal. See Section 5.6 “Wake-up Sources” SAM3S Summary 18 Single Supply Main Supply (1 ...
Page 19
... Backup mode is based on the Cortex-M3 deepsleep mode with the voltage regulator disabled. The SAM3S can be awakened from this mode through WUP0-15 pins, the supply monitor (SM), the RTT or RTC wake-up event. Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Con- trol Register of the Cortex-M3 set to 1 ...
Page 20
... This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with LPM = 0 in PMC_FSMR. The processor can be woke up from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the WFE instruction is used to enter this mode. SAM3S Summary 20 Section 5.7 “Fast Startup”). RTC or RTT Alarm and USB wake-up events Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective entry in Wait mode ...
Page 21
... WFE or WFI and/or Any Event (7) +SLEEPDEEP from: Fast start-up bit = 0 through WUP0-15 +LPM bit = 0 pins RTC alarm RTT alarm USB wake-up SAM3S Summary Table 5-1 below shows a summary PIO State Core at while in Low PIO State Consumption Wake Up Power Mode at Wake Up PIOA & ...
Page 22
... Wake-up Source SMEN sm_out RTCEN rtc_alarm RTTEN rtt_alarm WKUPT0 Falling/Rising WKUP0 Edge Detector WKUPT1 Falling/Rising WKUP1 Edge Detector WKUPT15 WKUPEN15 Falling/Rising WKUP15 Edge Detector SAM3S Summary 22 WKUPEN0 WKUPIS0 SLCK WKUPEN1 WKUPIS1 WKUPIS15 WKUPDBC WKUPS Debouncer 6500CS–ATARM–24-Jan-11 Core Supply Restart ...
Page 23
... Figure 5-5. WKUP0 WKUP1 WKUP15 6500CS–ATARM–24-Jan-11 Figure 5-5, is fully asynchronous and provides a fast start- Fast Start-Up Circuitry FSTT0 FSTP0 FSTT1 FSTP1 FSTT15 FSTP15 RTTAL RTT Alarm RTCAL RTC Alarm USBAL USB Alarm SAM3S Summary fast_restart 23 ...
Page 24
... The input output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAM3S embeds high speed pads able to handle MHz for HSMCI (MCK/2), 45 MHz for SPI clock lines and 35 MHz on other lines. See AC Characteristics Section in the Electrical Characteristics Section of the datasheet for more details. Typical pull-up and pull-down value is 100 kΩ ...
Page 25
... Low Level at startup PB10 - PB11 - PB7 - PB6 - PB5 - PB4 - XIN32 - XOUT32 - XIN - XOUT - Table 3-1 on page 6. SAM3S Summary Configuration (1) In Matrix User Interface Registers (Refer to the SystemIO Configuration Register in the Bus Matrix section of the product datasheet.) (2) See footnote below (3) See footnote below 25 ...
Page 26
... Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the “ ...
Page 27
... Table 7-1. Master 0 Master 1 Master 2 Master 3 7.4 Matrix Slaves The Bus Matrix of the SAM3S product manages 5 slaves. Each slave has its own arbiter, allow- ing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 6500CS– ...
Page 28
... TWI0 UART1 UART0 USART1 USART0 DAC SPI SSC HSMCI PIOA TWI1 TWI0 UART1 SAM3S Summary 28 SAM3S Master to Slave Access Masters Cortex-M3 I/D Internal SRAM Internal ROM Internal Flash External Bus Interface Peripheral Bridge Peripheral DMA Controller Channel T/R 100 & 64 Pins Transmit x Transmit x ...
Page 29
... Instrumentation Trace Macrocell (ITM) for support of printf style debugging • IEEE1149.1 JTAG Boundary-can on All Digital Pins 6500CS–ATARM–24-Jan-11 Peripheral DMA Controller (Continued) Channel T/R 100 & 64 Pins Receive Receive Receive Receive SPI Receive Receive Receive Receive SAM3S Summary 48 Pins ...
Page 30
... Product Mapping Figure 8-1. SAM3S Product Mapping Code 0x00000000 Boot Memory 0x00400000 1 MByte 1 MByte Internal Flash 0x00800000 bit band bit band Internal ROM 0x00C00000 Reserved 0x1FFFFFFF External RAM 0x60000000 SMC Chip Select 0 0x61000000 SMC Chip Select 1 0x62000000 SMC Chip Select 2 0x63000000 SMC Chip Select 3 ...
Page 31
... The Flash of the ATSAM3S4 (256-Kbytes internal Flash version) is organized in one bank of 1024 pages (Single plane) of 256 bytes. The Flash of the ATSAM3S2 (128-Kbytes internal Flash version) is organized in one bank of 512 pages (Single plane) of 256 bytes. The Flash of the ATSAM3S1 (64-Kbytes internal Flash version) is organized in one bank of 256 pages (Single plane) of 256 bytes ...
Page 32
... Security Bit Feature The SAM3S features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the command “ ...
Page 33
... Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default. 9.2 External Memories The SAM3S features an External Bus Interface to provide the interface to a wide range of exter- nal memories and to any parallel peripheral. 9.2.1 Static Memory Controller • ...
Page 34
... Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported • Additional Logic for NAND Flash SAM3S Summary 34 6500CS–ATARM–24-Jan-11 ...
Page 35
... MHz RC Main Clock Oscillator MAINCK Power Management MHz Controller XTAL Oscillator PLLACK MAINCK PLLA PLLBCK MAINCK PLLB SAM3S Summary Figure 10-1 on page 35. VDDOUT Software Controlled VDDIN Voltage Regulator VDDIO PIOA/B/C PIOx Input/Output Buffers Analog Comparator ADx ADC Analog Circuitry ADVREF ...
Page 36
... All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3S embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • ...
Page 37
... One 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller • One 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and to the peripherals. The PLLA input frequency is from 3 MHz. 6500CS–ATARM–24-Jan-11 SAM3S Summary 37 ...
Page 38
... The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at 4 MHz. The user can trim the 8 and 12 MHz RC Oscillator frequency by software. SAM3S Summary 38 Clock Generator On Chip 32 kHz ...
Page 39
... Figure 10-3. SAM3S Power Management Controller Block Diagram SLCK MAINCK PLLACK PLLBCK The SysTick calibration value is fixed at 8000 which allows the generation of a time base with SystTick clock at 8 MHz (max HCLK MHz/8). 10.7 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • Windowed, prevents the processor dead-lock on the watchdog access. ...
Page 40
... ATSAM3S2A (Rev A) ATSAM3S1A (Rev A) ATSAM3S4B (Rev A) ATSAM3S2B (Rev A) ATSAM3S1B (Rev A) ATSAM3S4C (Rev A) ATSAM3S2C (Rev A) ATSAM3S1C (Rev A) • JTAG ID: 0x05B2D03F SAM3S Summary 40 Controller restoration between interrupts. SAM3S Chip IDs Register Flash Size Chip Name (KBytes) 256 128 64 256 128 64 256 128 64 Pin Count ...
Page 41
... Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 6500CS–ATARM–24-Jan-11 Generator PIO available according to pin count 48 pin 64 pin SAM3S Summary 100 pin ...
Page 42
... TC0 24 TC1 25 TC2 26 TC3 27 TC4 28 TC5 29 ADC 30 DACC 31 PWM 32 CRCCU 33 ACC 34 UDP SAM3S Summary 42 defines the Peripheral Identifiers of the SAM3S. A peripheral identifier is required for NVIC Interrupt PMC Clock Control Instance Description ...
Page 43
... Peripheral Signal Multiplexing on I/O Lines The SAM3S product features 2 PIO controllers on 48-pin and 64-pin versions (PIOA, PIOB PIO controllers on the 100-pin version, (PIOA, PIOB, PIOC), that multiplex the I/O lines of the peripheral set. The SAM3S 64-pin and 100-pin PIO Controllers control lines. (See, line can be assigned to one of three peripheral functions ...
Page 44
... CTS1 PWMH2 PA26 DCD1 TIOA2 PA27 DTR1 TIOB2 PA28 DSR1 TCLK1 PA29 RI1 TCLK2 PA30 PWML2 NPCS2 PA31 NPCS1 PCK2 SAM3S Summary 44 Peripheral C Extra Function A17 WKUP0 A18 WKUP1 DATRG WKUP2 WKUP3 WKUP4 WKUP5 PWMFI0 WKUP6 WKUP7 WKUP8 WKUP14/PIODCEN1 PWML3 PWML2 ...
Page 45
... PB11 PB12 PWML1 PB13 PWML2 PB14 NPCS1 6500CS–ATARM–24-Jan-11 Peripheral C Extra Function NPCS2 AD6/ WKUP12 PCK2 PWMH2 PWML0 PCK0 PWMH3 SAM3S Summary System Function AD4 AD5 AD7 TDI WKUP13 TDO/TRACESWO TMS/SWDIO TCK/SWCLK XOUT XIN DDM DDP ERASE DAC0 DAC1 ...
Page 46
... PC20 A2 PC21 A3 PC22 A4 PC23 A5 PC24 A6 PC25 A7 PC26 A8 PC27 A9 PC28 A10 PC29 A11 PC30 A12 PC31 A13 SAM3S Summary 46 Peripheral C Extra Function PWML0 PWML1 PWML2 PWML3 NPCS1 PWML0 PWML1 PWMH0 PWMH1 PWMH2 PWMH3 PWML3 TIOA3 TIOB3 TCLK3 TIOA4 TIOB4 TCLK4 TIOA5 TIOB5 ...
Page 47
... Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter 6500CS–ATARM–24-Jan-11 peripherals Sensors and data per chip select Generator SAM3S Summary 2 C compatible devices 47 ...
Page 48
... Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 12.6 Timer Counter (TC) • Six 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting SAM3S Summary TDM Buses, Magnetic Card Reader) 6500CS–ATARM–24-Jan-11 ...
Page 49
... Mode to update the synchronous channels registers after a programmable number • Connection to one PDC channel – Offers Buffer transfer without Processor Intervention, to update duty cycle of • independent event lines which can send triggers on ADC within a period 6500CS–ATARM–24-Jan-11 channel of periods synchronous channels SAM3S Summary 49 ...
Page 50
... Pull-down resistor on DDM and DDP when disabled 12.10 Analog-to-Digital Converter (ADC) • Channels, • 10/12-bit resolution • MSample/s • programmable sequence of conversion on each channel • Integrated temperature sensor • Single ended/differential conversion SAM3S Summary 50 6500CS–ATARM–24-Jan-11 ...
Page 51
... High speed option vs. low power option • Selectable input hysteresis: – mV • Minus input selection: – DAC outputs – Temperature Sensor – ADVREF – AD0 to AD3 ADC channels • Plus input selection: – All analog inputs 6500CS–ATARM–24-Jan-11 SAM3S Summary 51 ...
Page 52
... Interrupt on: – Rising edge, Falling edge, toggle 12.14 Cyclic Redundancy Check Calculation Unit (CRCCU) • 32-bit cyclic redundancy check automatic calculation • CRC calculation between two addresses of the memory SAM3S Summary 52 6500CS–ATARM–24-Jan-11 ...
Page 53
... Package Drawings The SAM3S series devices are available in LQFP, QFN and LFBGA packages. Figure 13-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. 6500CS–ATARM–24-Jan-11 SAM3S Summary 53 ...
Page 54
... Figure 13-2. 100-ball LFBGA Package Drawing SAM3S Summary 54 6500CS–ATARM–24-Jan-11 ...
Page 55
... Figure 13-3. 64- and 48-lead LQFP Package Drawing 6500CS–ATARM–24-Jan-11 SAM3S Summary 55 ...
Page 56
... Symbol θ 1 θ 2 θ aaa bbb ccc ddd SAM3S Summary 56 48-lead LQFP Package Dimensions (in mm) Millimeter Min Nom Max – – 1.60 0.05 – 0.15 1.35 1.40 1.45 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.08 – 0.20 0.08 – – 0° 3.5° 7° ...
Page 57
... REF 0.20 – 0.17 0.20 0.50 BSC. 7.50 7.50 Tolerances of Form and Position 0.20 0.20 0.08 0.08 SAM3S Summary Inch Max Min Nom 1.60 – – 0.15 0.002 – 1.45 0.053 0.055 0.472 BSC 0.383 BSC 0.472 BSC 0.383 BSC 0.20 0.003 – – 0.003 – 7° ...
Page 58
... Figure 13-4. 48-pad QFN Package SAM3S Summary 58 6500CS–ATARM–24-Jan-11 ...
Page 59
... REF 0.18 0.20 0.23 7.00 bsc 5.45 5.60 5.75 7.00 bsc 5.45 5.60 5.75 0.35 0.40 0.45 0.50 bsc 0.09 – – Tolerances of Form and Position 0.10 0.10 0.05 SAM3S Summary Inch Min Nom Max – – 0.035 – – 0.002 – 0.026 0.028 0.008 REF 0.007 0.008 0.009 0.276 bsc 0.215 0.220 0.226 0.276 bsc 0.215 0.220 0.226 ...
Page 60
... Figure 13-5. 64-pad QFN Package Drawing SAM3S Summary 60 6500CS–ATARM–24-Jan-11 ...
Page 61
... Ordering Information Table 14-1. Ordering Codes for SAM3S Devices Ordering Code MRL ATSAM3S4CA-AU A ATSAM3S4CA-CU A ATSAM3S4BA-AU A ATSAM3S4BA-MU A ATSAM3S4AA-AU A ATSAM3S4AA-MU A ATSAM3S2CA-AU A ATSAM3S2CA-CU A ATSAM3S2BA-AU A ATSAM3S2BA-MU A ATSAM3S2AA-AU A ATSAM3S2AA-MU A ATSAM3S1CA-AU A ATSAM3S1CA-CU A ATSAM3S1BA-AU A ATSAM3S1BA-MU A ATSAM3S1AA-AU A ATSAM3S1AA-MU A 6500CS–ATARM–24-Jan-11 Flash (Kbytes) Package (Kbytes) 256 QFP100 256 BGA100 ...
Page 62
... Figure 5-1, "Single Supply",Figure 5-2, "Core Externally Supplied" 6500BS Figure 5-2, "Core Externally supply is 2.0V-3.6V. Section 12.13 “Analog removed. Section 9.1.3.8 “Unique 6500AS First issue SAM3S Summary 62 Table 4-1, “100-lead LQFP SAM3S4/2/1C Pinout” Pinout”. updated. Description”. 14-1. Section 10.5 “Clock Generator”. Section 5.5.2 “Wait Mode”. ® Section 9.1.3.10 “SAM-BA Boot” ...
Page 63
... SAM3S Summary 63 ...
Page 64
Headquarters International Atmel Corporation Atmel Asia 2325 Orchard Parkway Unit 1-5 & 16, 19/F San Jose, CA 95131 BEA Tower, Millennium City 5 USA 418 Kwun Tong Road Tel: 1(408) 441-0311 Kwun Tong, Kowloon Fax: 1(408) 487-2600 Hong Kong Tel: ...