SAM3S2C Atmel Corporation, SAM3S2C Datasheet - Page 68
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SAM3S2C
Manufacturer Part Number
SAM3S2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.6.6
10.6.7
10.6.7.1
10.6.7.2
68
SAM3S
Interrupt priority grouping
Exception entry and return
Preemption
Return
Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and
NMI exceptions, with fixed negative priority values, always have higher priority than any other
exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1]
means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1]
is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest
exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and
have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception
being handled, the handler is not preempted, irrespective of the exception number. However,
the status of the new interrupt changes to pending.
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
divides each interrupt priority register entry into two fields:
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler,
If multiple pending interrupts have the same group priority, the subpriority field determines the
order in which they are processed. If multiple pending interrupts have the same group priority
and subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
“Application Interrupt and Reset Control Register” on page
Descriptions of exception handling use the following terms:
When the processor is executing an exception handler, an exception can preempt the exception
handler if its priority is higher than the priority of the exception being handled. See
ority grouping” on page 68
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception entry” on page 69
This occurs when the exception handler is completed, and:
The processor pops the stack and restores the processor state to the state it had before the
interrupt occurred. See
• an upper field that defines the group priority
• a lower field that defines a subpriority within the group.
• there is no pending exception with sufficient priority to be serviced
• the completed exception handler was not handling a late-arriving exception.
“Exception return” on page 70
for more information about preemption by an interrupt.
more information.
for more information.
171.
6500C–ATARM–8-Feb-11
“Interrupt pri-
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