SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 103
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SAM7S16
Manufacturer Part Number
SAM7S16
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S16
Flash (kbytes)
16 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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3.10
ARM DDI 0029G
Reset sequence after power up
nRESET
nMREQ
D[31:0]
nEXEC
A[31:0]
It is good practice to reset a static device immediately on power-up, to remove any
undefined conditions within the device that can otherwise combine to cause a DC path
and consequently increase current consumption. Most systems are reset by using a
simple RC circuit on the reset pin to remove the undefined states within devices whilst
clocking the device.
During reset, the signals nMREQ and SEQ show internal cycles where the address bus
continues to increment by two or four bytes. The initial address and increment values
are determined by the state of the core when nRESET was asserted. They are undefined
after power up.
After nRESET has been taken HIGH, the ARM core does two further internal cycles
before the first instruction is fetched from the reset vector (address
takes three MCLK cycles to advance this instruction through the
Fetch-Decode-Execute stages of the ARM instruction pipeline before this first
instruction is executed. This is shown in Figure 3-22.
nRESET must be held asserted for a minimum of two MCLK cycles to fully reset the
core.
You must reset the EmbeddedICE Logic and the TAP controller as well, whether the
debug features are used or are not. This is done by taking nTRST LOW for at least T
no later than nRESET.
In Figure 3-22, x, y, and z are incrementing address values.
MCLK
SEQ
Note
Copyright © 1994-2001. All rights reserved.
x
y
z
Fetch 1
0
Figure 3-22 Reset sequence
Decode 1
4
Memory Interface
Execute 1
). It then
8
3-33
bsr
,
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