SAM7S161 Atmel Corporation, SAM7S161 Datasheet - Page 45

• Manufacturer Part Number: SAM7S161
• Manufacturer: Atmel Corporation

Specifications of SAM7S161

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.2.6
6175L–ATARM–28-Jul-11
Thumb Instruction Set Overview
Table 11-2.
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same
physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also
access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the
Mnemonic
MOV
ADD
SUB
RSB
CMP
TST
AND
EOR
MUL
SMULL
SMLAL
MSR
B
BX
LDR
LDRSH
LDRSB
LDRH
LDRB
LDRBT
LDRT
LDM
SWP
MCR
LDC
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store Multiple instructions
• Exception-generating instruction
ARM Instruction Mnemonic List
Operation
Move
Add
Subtract
Reverse Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Multiply
Sign Long Multiply
Signed Long Multiply Accumulate
Move to Status Register
Branch and Exchange
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Load Register Byte with Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Branch
STM
STC
Mnemonic
CDP
MVN
ADC
SBC
RSC
CMN
TEQ
BIC
ORR
MLA
UMULL
UMLAL
MRS
BL
SWI
STR
STRH
STRB
STRBT
STRT
SWPB
MRC
Operation
Coprocessor Data Processing
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
Test Equivalence
Bit Clear
Logical (inclusive) OR
Multiply Accumulate
Unsigned Long Multiply
Unsigned Long Multiply Accumulate
Move From Status Register
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Store Register Byte with Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
SAM7S Series
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