SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 246
SAM7S256
Manufacturer Part Number
SAM7S256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B-28
DBGACK
nMREQ
SEQ
D[31:0]
A[31:0]
CLK
You can see from Figure 5-3 on page 5-7 that the final memory access occurs in the
cycle after DBGACK goes HIGH, this is the point at which the cycle counter must be
disabled. Figure B-6 shows that the first memory access that the cycle counter has not
seen before occurs in the cycle after DBGACK goes LOW and so this is when the
counter must be re-enabled.
When a system speed access from debug state occurs, the core temporarily drops out of
debug state and so DBGACK can go LOW. If there are peripherals that are sensitive to
the number of memory accesses, they must be led to believe that the core is still in debug
state. By programming the EmbeddedICE macrocell control register, the value on
DBGACK can be forced to be HIGH.
Internal cycles
Note
Copyright © 1994-2001. All rights reserved.
N
Ab
S
Ab+4 Ab+8
Figure B-6 Debug exit sequence
S
ARM DDI 0029G
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