SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 65
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SAM7S256
Manufacturer Part Number
SAM7S256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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2.8.5
2.8.6
ARM DDI 0029G
Interrupt request
Abort
The Interrupt Request (IRQ) exception is a normal interrupt caused by a LOW level on
the nIRQ input. IRQ has a lower priority than FIQ, and is masked on entry to an FIQ
sequence. As with the nFIQ input, nIRQ passes into the core through a synchronizer.
Irrespective of whether exception entry is from ARM state or Thumb state, an IRQ
handler returns from the interrupt by executing:
You can disable IRQ at any time, by setting the I bit in the CPSR from a privileged
mode.
An abort indicates that the current memory access cannot be completed. An abort is
signaled by the external ABORT input. The ARM7TDMI processor checks for the abort
exception at the end of memory access cycles.
The abort mechanism allows the implementation of a demand-paged virtual memory
system. In such a system, the processor is allowed to generate arbitrary addresses. When
the data at an address is unavailable, the Memory Management Unit (MMU) signals an
abort.
The abort handler must then:
•
•
The application program needs no knowledge of the amount of memory available to it,
nor is its state in any way affected by the abort.
There are two types of abort:
•
•
Work out the cause of the abort and make the requested data available.
Load the instruction that caused the abort using an
instruction to determine whether that instruction specifies base register
write-back. If it does, the abort handler must then:
—
—
This ensures that when the instruction is retried, the base register will have been
restored to the value it had when the instruction was originally executed.
a Prefetch Abort occurs during an instruction prefetch
a Data Abort occurs during a data access.
Copyright © 1994-2001. All rights reserved.
determine from the instruction what the offset applied to the base register
by the write-back was
apply the opposite offset to the value that will be reloaded into the base
register when the abort handler returns.
Programmer’s Model
2-19
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