SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 205

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

23.6.2
6222F–ATARM–14-Jan-11
SDRAM Controller Read Cycle
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the transfer type signal provided by the master requesting the access. If
the next access is a sequential read access, reading to the SDRAM device is carried out. If the
next access is a sequential read access, but the current access is to a boundary page, or if the
next access is in another row, then the SDRAM Controller generates a precharge command,
activates the new row and initiates a read command. To comply with SDRAM timing parameters,
an additional clock cycle is inserted between the precharge/active (t
active/read (t
ply with CAS latency. The SDRAM Controller supports a CAS latency of two. For definition of
these timing parameters, refer to
described in
Figure 23-4. Read Burst, 32-bit SDRAM access
D[31:0]
A[12:0]
SDCS
SDWE
(Input)
SDCK
RAS
CAS
RCD
Figure 23-4
) command, After a read command, additional wait states are generated to com-
Row n
below.
t
RCD
= 3
col a
“SDRAMC Configuration Register” on page
CAS = 2
col b
Dna
col c
Dnb
col d
SAM7SE512/256/32
Dnc
col e
Dnd
col f
RP
Dne
) command and the
Dnf
213. This is
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