SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 470
SAM7SE256
Manufacturer Part Number
SAM7SE256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7SE256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
48 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
88
Ext Interrupts
88
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Figure 35-8. Transmitter Block Diagram
35.6.3
470
Transmitter Clock
SAM7SE512/256/32
Receiver Operations
SSC_TFMR.DATLEN
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
RF
Selector
Start
TF
A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR).
“Start” on page 471.
The frame synchronization is configured setting the Receive Frame Mode Register
(SSC_RFMR).
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the SSC_RCMR. The data is transferred from the shift register depending on the
data format selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the sta-
tus flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If
another transfer occurs before read of the RHR register, the status flag OVERUN is set in
SSC_SR and the receiver shift register is transferred in the RHR register.
SSC_TFMR.MSBF
SSC_THR
SSC_TFMR.DATDEF
See “Frame Sync” on page 473.
Transmit Shift Register
0
1
SSC_TSHR
1
0
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_TFMR.FSLEN
SSC_CR.TXEN
SSC_CR.TXDIS
SSC_SR.TXEN
6222F–ATARM–14-Jan-11
TD
See
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