SAM7SE512 Atmel Corporation, SAM7SE512 Datasheet - Page 63

• Manufacturer Part Number: SAM7SE512
• Manufacturer: Atmel Corporation

Specifications of SAM7SE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.8.2
ARM DDI 0029G
Exception
or entry
FIQ
IRQ
DABT
RESET
Entering an exception
Return instruction
Not applicable
The ARM7TDMI processor handles an exception as follows:
1.
2.
3.
4.
The ARM7TDMI processor can also set the interrupt disable flags to prevent otherwise
unmanageable nestings of exceptions.
Preserves the address of the next instruction in the appropriate LR.
When the exception entry is from ARM state, the ARM7TDMI processor copies
the address of the next instruction into the LR, current PC+4 or PC+8 depending
on the exception.
When the exception entry is from Thumb state, the ARM7TDMI processor writes
the value of the PC into the LR, offset by a value, current PC+4 or PC+8
depending on the exception, that causes the program to resume from the correct
place on return.
The exception handler does not have to determine the state when entering an
exception. For example, in the case of a SWI,
the next instruction regardless of whether the SWI was executed in ARM or
Thumb state.
Copies the CPSR into the appropriate SPSR.
Forces the CPSR mode bits to a value that depends on the exception.
Forces the PC to fetch the next instruction from the relevant exception vector.
Copyright © 1994-2001. All rights reserved.
Previous state ARM r14_x
Thumb r14_x
PC+4
PC+4
PC+8
-
PC+4
PC+4
PC+8
-
Table 2-3 Exception entry and exit (continued)
Remarks
Where PC is the address of the instruction
that was not executed because the FIQ or
IRQ took priority
Where PC is the address of the Load or Store
instruction that generated the Data Abort
The value saved in r14_svc upon reset is
unpredictable
Programmer’s Model
always returns to
2-17