SAM7X512 Atmel Corporation, SAM7X512 Datasheet - Page 82

• Manufacturer Part Number: SAM7X512
• Manufacturer: Atmel Corporation

Specifications of SAM7X512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
3.4.4
3-12
nOPC
The address produced by the processor is always a byte address. However, the memory
system must ignore the bottom redundant bits of the address. The significant address
bits are listed in Table 3-3.
The size of transfer does not change during a burst of S-cycles.
The ARM7TDMI processor cannot generate bursts of byte transfers.
During instruction accesses the redundant address bits are undefined. The memory
system must ignore these redundant bits.
A writable memory system for the ARM7TDMI processor must have individual byte
write enables. Both the C Compiler and the ARM debug tool chain, for example,
Multi-ICE, assume that arbitrary bytes in the memory can be written. If individual byte
write capability is not provided, you might not be able to use either of these tools
without data corruption.
The nOPC output conveys information about the transfer. An MMU can use this signal
to determine whether an access is an opcode fetch or a data transfer. This signal can be
used with nTRANS to implement an access permission scheme. The meaning of nOPC
is listed in Table 3-4.
Note
Copyright © 1994-2001. All rights reserved.
MAS[1:0]
00
01
10
11
nOPC
0
1
Width
Byte
Halfword
Word
Reserved
Table 3-3 Significant address bits
Significant address bits
A[31:0]
A[31:1]
A[31:2]
-
Opcode/data
Opcode
Data
Table 3-4 nOPC
ARM DDI 0029G