SAM7X512 Atmel Corporation, SAM7X512 Datasheet

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... In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes (SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) • ...

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... VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector • Fully Static Operation MHz at 1.65V and 85⋅ C Worst Case Conditions • Available in 100-lead LQFP Green and 100-ball TFBGA Green Packages SAM7X512/256/128 Summary 2 ® Infrared Modulation/Demodulation 2 C Compatible Devices Supported ...

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... Description Atmel's SAM7X512/256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbytes high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. A complete set of system functions minimizes the number of external components. ...

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... SAM7X512/256/128 Block Diagram Figure 2-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADVREF SAM7X512/256/128 Summary 4 SAM7X512/256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK System Controller TST FIQ ...

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... Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ1 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - PA30 Parallel IO Controller A PB0 - PB30 Parallel IO Controller B 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary Active Type Level Power Power Power Power Power Power Power Ground ...

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... Master In Slave Out SPIx_MOSI Master Out Slave In SPIx_SPCK SPI Serial Clock SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select TWD Two-wire Serial Data TWCK Two-wire Serial Clock SAM7X512/256/128 Summary 6 Active Type USB Device Port Analog Analog USART I/O I/O Input Output Input ...

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... ECOL Collision Detected EMDC Management Data Clock EMDIO Management Data Input/Output EF100 Force 100 Mbits/sec. Note: 1. Refer to Section 6. ”I/O Lines 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary Type Analog-to-Digital Converter Analog Analog Input Analog Fast Flash Programming Interface Input Input I/O Output ...

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... Package The SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS-com- pliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 tion is given in the Mechanical Characteristics section. Figure 4-1. SAM7X512/256/128 Summary 8 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip- 100-lead LQFP Package Outline (Top View) ...

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... VDDIO 42 18 PA10/PGMM2 43 19 PA11/PGMM3 44 20 PA12/PGMD0 45 21 PA13/PGMD1 46 22 PA14/PGMD2 47 23 PA15/PGMD3 48 24 PA16/PGMD4 49 25 PA17/PGMD5 50 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary PA18/PGMD6 51 PB9 52 PB8 53 PB14 54 PB13 55 PA23/PGMD11 PB6 56 PA24/PGMD12 GND 57 VDDIO 58 PB5 59 PA25/PGMD13 PB15 60 PA26/PGMD14 PB17 61 VDDCORE 62 PB7 ...

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... E4 B10 PA17/PGMD5 E5 C1 PB16 E6 C2 PB4 E7 C3 PB10 E8 C4 PB3 E9 C5 PB0 E10 SAM7X512/256/128 Summary 10 shows the orientation of the 100-ball TFBGA package. A detailed mechanical 100-ball TFBGA Package Outline (Top View BALL A1 Signal Name Pin Signal Name ...

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... Power Consumption The SAM7X512/256/128 has a static current of less than 60 µA on VDDCORE at 25°C, includ- ing the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current. ...

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... Typical Powering Schematics The SAM7X512/256/128 supports a 3.3V single supply mode. The internal regulator input con- nected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. the power schematics to be used for USB bus-powered systems. Figure 5-1. SAM7X512/256/128 Summary 12 3.3V System Single Power Supply Schematic ...

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... SAM7X512/256/128 when asserted high. The TST pin integrates a permanent pull-down resis- tor of about 15 kΩ ...

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... The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA. SAM7X512/256/128 Summary 14 6120GS–ATARM–07-Apr-11 ...

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... Facilitates debug by detection of bad pointers • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap Command – Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary Controller 15 ...

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... One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements • Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest): SAM7X512/256/128 Summary 16 wait states Receive ...

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... Full chip erase time – 10,000 write cycles, 10-year data retention capability – 8 lock bits, each protecting 8 sectors of 64 pages – Protection Mode to secure contents of the Flash • 32 Kbytes of Fast SRAM – Single-cycle access at full speed 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary 17 ...

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... Figure 8-1. SAM7X512/256/128 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF SAM7X512/256/128 Summary 18 Internal Memory Mapping 0x0000 0000 ...

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... After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The SAM7X512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA program. 8.4.3 Internal Flash • ...

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... Embedded Flash 8.5.1 Flash Overview • The Flash of the SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the SAM7X256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words. ...

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... Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.5.4 Security Bit Feature The SAM7X512/256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command “ ...

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... The SAM-BA Boot is in ROM and is mapped at address 0x0 when the GPNVM Bit 2 is set to 0. When GPNVM bit 2 is set to 1, the device boots from the Flash. When GPNVM bit 2 is set to 0, the device boots from ROM (SAM-BA). SAM7X512/256/128 Summary 22 6120GS–ATARM–07-Apr-11 ...

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... Figure 9-1 on page 24 Figure 8-1 on page 18 erals. Note that the Memory Controller configuration user interface is also mapped within this address space. 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary shows the System Controller Block Diagram. shows the mapping of the User Interface of the System Controller periph- 23 ...

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... Figure 9-1. NRST XIN XOUT PLLRC PA0-PA30 PB0-PB30 SAM7X512/256/128 Summary 24 System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset Timer SLCK Real-Time ...

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... Brownout Detector and Power-on Reset The SAM7X512/256/128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the power supplies. ...

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... RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2. SAM7X512/256/128 Summary 26 Clock Generator Block Diagram Clock Generator Embedded RC ...

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... Programmable positive/negative edge-triggered or high/low level-sensitive external • 8-level Priority Controller – Drives the normal interrupt nIRQ of the processor – Handles priority of the interrupt sources 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4, ...

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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x275C 0A40 (MRL A) for SAM7X512 – Chip ID is 0x275B 0940 (MRL for SAM7X256 – Chip ID is 0x275B 0942 (MRL C) for SAM7X256 – ...

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... Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary 29 ...

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... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 Peripheral Identifiers The SAM7X512/256/128 embeds a wide range of peripherals. Identifiers of the SAM7X512/256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID 0 ...

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... Peripheral Multiplexing on PIO Lines The SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral func- tions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...

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... CANRX PA20 CANTX PA21 TF PA22 TK PA23 TD PA24 RD PA25 RK PA26 RF PA27 DRXD PA28 DTXD PA29 FIQ PA30 IRQ0 SAM7X512/256/128 Summary 32 Peripheral B Comments High-Drive High-Drive SPI1_NPCS1 High-Drive SPI1_NPCS2 High-Drive SPI1_NPCS3 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 PCK1 IRQ1 TCLK2 SPI1_NPCS0 SPI1_SPCK SPI1_MOSI SPI1_MISO SPI1_NPCS1 SPI1_NPCS2 PCK3 ...

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... PWM3 PB23 TIOA0 PB24 TIOB0 PB25 TIOA1 PB26 TIOB1 PB27 TIOA2 PB28 TIOB2 PB29 PCK1 PB30 PCK2 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary Peripheral B Comments PCK0 SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2 SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 ...

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... Programmable delay between consecutive transfers – Selectable mode fault detection – Maximum frequency Master Clock 10.8 Two-wire Interface • Master Mode only • Compatibility with I SAM7X512/256/128 Summary 34 peripherals Sensors between clock and data 2 C compatible devices (refer to the TWI section of the datasheet) ® ...

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... Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.11 Timer Counter • Three 16-bit Timer Counter Channels – Two output compare or one input capture per channel • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary 35 ...

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... Endpoint 0: 8 bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Endpoint 4 and 5: 256 bytes ping-pong – Ping-pong Mode (two memory banks) for bulk endpoints • Suspend/resume logic SAM7X512/256/128 Summary 36 Table 10-4 Timer Counter Clocks Assignment Clock MCK/2 ...

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... Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Four of eight analog inputs shared with digital signals 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary enabled channels 37 ...

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... Package Drawings Figure 11-1. LQFP Package Drawing SAM7X512/256/128 Summary 38 6120GS–ATARM–07-Apr-11 ...

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... θ1 θ2 θ aaa bbb ccc ddd 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary 100-lead LQFP Package Dimensions Millimeter Min Nom Max 1.60 0.05 0.15 1.35 1.40 1.45 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.08 0.20 0.08 0° 3.5° 7° 0° 11° 12° 13° ...

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... Figure 11-2. TFBGA Package Drawing All dimensions are in mm SAM7X512/256/128 Summary 40 6120GS–ATARM–07-Apr-11 ...

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... MLR B Ordering Code Ordering Code AT91SAM7X512-AU AT91SAM7X512-CU AT91SAM7X256-AU AT91SAM7X256B-AU AT91SAM7X256-CU AT91SAM7X256B-CU AT91SAM7X128-AU AT91SAM7X128B-AU AT91SAM7X128-CU AT91SAM7X128B-CU 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary MLR C Ordering Code – AT91SAM7X256C-AU AT91SAM7X256C-CU AT91SAM7X128C-AU AT91SAM7X128C-CU Package Package Type Operating Range LQFP 100 Green (-40⋅ 85⋅ C) TFBGA 100 ...

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... Update to product functionalities including changes to Section 9.5 “Debug Unit” on page 28 Updated PLL output range max value in Updated information in Updated ordering information in 6120DS Added AT91SAM7X512 to product Reformatted Memories Reordered sub sections in Peripherals Consolidated Memory Mapping in Added TFBGA information added LQFP and TFBGA package drawings System Controller block diagram “ ...

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... Except for part ordering and library references, AT91 prefix dropped from most nomenclature. AT91SAM7X becomes SAM7X. 6120GS–ATARM–07-Apr-11 SAM7X512/256/128 Summary Interface”, updated. Controller”, added PDC priority list. Counter”, The TC has Two output compare or one input capture per channel. ...

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