SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 14

• Manufacturer Part Number: SAM7XC512
• Manufacturer: Atmel Corporation

Specifications of SAM7XC512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6. I/O Lines Considerations
6.1
6.2
6.3
6.4
6.5
14
JTAG Port Pins
Test Pin
Reset Pin
ERASE Pin
PIO Controller Lines
AT91SAM7XC512/256/128
TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not
integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ.
To eliminate any risk of spuriously entering the JTAG boundary scan mode due to noise on
JTAGSEL, it should be tied externally to GND if boundary scan is not used, or pulled down with
an external low-value resistor (such as 1 kΩ) .
T h e T S T p i n i s u s e d f o r m a n u f a c t u r i n g t e s t o r f a s t p r o g r a m m i n g m o d e o f t h e
AT91SAM7XC512/256/128 when asserted high. The TST pin integrates a permanent pull-down
resistor of about 15 kΩ to GND.
To eliminate any risk of entering the test mode due to noise on the TST pin, it should be tied to
GND if the FFPI is not used, or pulled down with an external low-value resistor (such as 1 kΩ) .
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied to low.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset
controller and can be driven low to provide a reset signal to the external components or asserted
low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,
and the reset controller can guarantee a minimum pulse length. This allows connection of a sim-
ple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset
all the components of the system.
The NRST pin integrates a permanent pull-up resistor to VDDIO.
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 kΩ to GND.
To eliminate any risk of erasing the Flash due to noise on the ERASE pin, it shoul be tied exter-
nally to GND, which prevents erasing the Flash from the applicatiion, or pulled down with an
external low-value resistor (such as 1 kΩ) .
This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing
time is 200 ms.
All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programma-
ble pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO controllers.
6209DS–ATARM–17-Feb-09