SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 46

• Manufacturer Part Number: SAM7XC512
• Manufacturer: Atmel Corporation

Specifications of SAM7XC512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Revision History
Table 13-1.
46
Doc. Rev
6209S
6209BS
6209CS
6209DS
AT91SAM7XC512/256/128
Comments
First issue - Unqualified on Intranet
Legal page updated.Qualified on Intranet
Added AT91SAM7XC512 to product
Reformatted Memories
Reordered sub sections in Peripherals
Consolidated Memory Mapping in
Added package drawings
Consolidated Memory Mapping in
Added TFBGA information
page 10
Added LQFP and TFBGA package drawings
System Controller block diagram
“Features”, TWI updated to include Atmel TWI compatibility with I
“Features”,
Section 10.8 ”Two-wire
Section 10.11 ”Timer
Section 10.17 ”Analog-to-Digital
Figure 3-1,”Signal Description
Section 6.1 ”JTAG Port
Figure 9-1,”System Controller Block
Figure 8-1,”AT91SAM7XC512/256/128 Memory
Section 8.4.3 ”Internal
the Remap Command.”
Section 12. ”AT91SAM7XC512/256/128 Ordering
information.
Revision History
and
“Debug Unit (DBGU)”
“Features” on page 1
≤
Counter”,The TC has Two output compare or one input capture per channel.
Flash”,updated: “At any time, the Flash is mapped ... if GPNVM bit 2 is set and before
Section 8. “Memory” on page
Interface”, updated.
Pins”,
Section 11. “Package Drawings” on page
Section 4.3 “100-ball TFBGA Package Outline” on page
Section 6.2 ”Test Pin”
List”, footnote added to JTAGSEL, ERASE and TST pin comments
Converter”,INL and DNL updated.
Figure 9-1 on page
added
Figure 8-1 on page
Figure 8-1 on page
Diagram”, RTT is reset by power_on_reset.
family.“Features” on page 1
Section 10. “Peripherals” on page 32
“Mode for General Purpose 2-wire UART Serial
Section 11. on page
Mapping”,TDES base address is 0xFFFA 8000
Information”, MLR B chip revision added to ordering
and
26, “ice_nreset” signals changed to “power_on_reset”.
18.
19.
19.
Section 6.4 ”ERASE
and global
2
42.
C Standard.
42.
Pin”updated.
11. and
Communication”.
Section 4.4 on
6209DS–ATARM–17-Feb-09
Change
Request
Ref.
2729
4247
5846
4211
4008
5068
5225
5257
5850
6064