SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 61
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SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
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- Download datasheet (2Mb)
2.7.3
ARM DDI 0029G
M[4:0]
10000
10001
10010
10011
10111
11011
11111
Reserved bits
Mode
User
FIQ
IRQ
Supervisor
Abort
Undefined
System
Mode bits
Bits M[4:0] determine the processor operating mode as shown in Table 2-2. Not all
combinations of the mode bits define a valid processor mode, so take care to use only
the bit combinations shown.
An illegal value programmed into M[4:0] causes the processor to enter an
unrecoverable state. If this occurs, apply reset.
The remaining bits in the PSRs are unused, but are reserved. When changing a PSR flag
or control bits, make sure that these reserved bits are not altered. Also, make sure that
your program does not rely on reserved bits containing specific values because future
processors might have these bits set to 1 or 0.
Visible Thumb-state registers
r0–r7, SP, LR, PC, CPSR
r0–r7, SP_fiq, LR_fiq, PC, CPSR, SPSR_fiq
r0–r7, SP_irq, LR_irq, PC, CPSR, SPSR_irq
r0–r7, SP_svc, LR_svc, PC, CPSR,
SPSR_svc
r0–r7, SP_abt, LR_abt, PC, CPSR,
SPSR_abt
r0–r7, SP_und, LR_und, PC, CPSR,
SPSR_und
r0–r7, SP, LR, PC, CPSR
Copyright © 1994-2001. All rights reserved.
Visible ARM-state registers
r0–r14, PC, CPSR
r0–r7, r8_fiq–r14_fiq, PC, CPSR,
SPSR_fiq
r0–r12, r13_irq, r14_irq, PC, CPSR,
SPSR_irq
r0–r12, r13_svc, r14_svc, PC, CPSR,
SPSR_svc
r0–r12, r13_abt, r14_abt, PC, CPSR,
SPSR_abt
r0–r12, r13_und, r14_und, PC, CPSR,
SPSR_und
r0–r14, PC, CPSR
Table 2-2 PSR mode bit values
Programmer’s Model
2-15
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