SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 69
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SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
- Current page: 69 of 284
- Download datasheet (2Mb)
2.9
2.9.1
2.9.2
ARM DDI 0029G
Interrupt latencies
Maximum interrupt latencies
Minimum interrupt latencies
The calculations for maximum and minimum latency are described in:
•
•
When FIQs are enabled, the worst-case latency for FIQ comprises a combination of:
•
•
•
•
The total latency is therefore 29 processor cycles, just over 0.7 microseconds in a
system that uses a continuous 40MHz processor clock. At the end of this time, the
ARM7TDMI processor executes the instruction at
The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ,
having higher priority, can delay entry into the IRQ handling routine for an arbitrary
length of time.
The minimum latency for FIQ or IRQ is the shortest time the request can take through
the synchronizer, T
Maximum interrupt latencies on page 2-23
Minimum interrupt latencies on page 2-23.
The longest time the request can take to pass through the synchronizer, T
(four processor cycles).
The time for the longest instruction to complete, T
an LDM which loads all the registers including the PC. T
wait state system.
The time for the Data Abort entry, T
The time for FIQ entry, T
Copyright © 1994-2001. All rights reserved.
syncmin
, plus T
fiq
fiq
(two cycles).
, a total of five processor cycles.
exc
(three cycles).
.
ldm
. The longest instruction, is
ldm
is 20 cycles in a zero
Programmer’s Model
syncmax
2-23
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